Semiconductor device manufacturing method and mask manufacturing method

• US 10,223,494 B2
• Filed: 07/25/2016
• Issued: 03/05/2019
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, So-eun, Park, Ji-soong, Lee, Suk-ho, Shon, Jung-wook
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US15/219,142
• Publication Number:
  US 20170024510A1
• Time in Patent Office: 953 Days
• Field of Search: 716 52- 53
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of manufacture comprises a mask process correction (MPC) and verifying MPC accuracy. MPC may be performed on mask tape-out (MTO) data describing a mask pattern to obtain mask process corrected data. MPC may be performed to address a deviation between the MTO data and a mask to be manufactured. Verification of the MPC may be performed by generating a two-dimensional (2D) contour of mask pattern elements based on the mask process corrected data. When MPC has been verified, the mask process corrected data may be used to manufacture a mask and a semiconductor device.

Claims

1. A manufacturing method comprising:

performing a mask process correction (MPC) on mask tape-out (MTO) design data describing a first mask pattern by applying the MPC to the MTO design data to obtain mask process corrected data describing a second mask pattern;

verifying the performance of the MPC by generating a two-dimensional (2D) contour of one or more mask pattern elements of a photolithography mask by performing a simulation of manufacturing the one or more mask pattern elements of the photolithography mask described by the mask process corrected data using a mask process model that models a photolithography mask manufacturing process; and

manufacturing at least one of a mask and a semiconductor device in response to the verifying,

wherein the MPC is responsive to the mask process model and the mask process model is adjustable based on the verifying, and

wherein verifying the MPC comprises comparing the 2D contour with a shape of one or more mask patterns with corresponding one or more mask patterns represented by the MTO design data.

2. The manufacturing method of claim 1, wherein the generating of the 2D contour comprises applying a simulation transformation function to the mask process corrected data.

3. The manufacturing method of claim 1, wherein the manufacturing of at least one of a mask and a semiconductor device includes manufacturing a photolithography mask with process parameters described by the mask process model.

4. The manufacturing method of claim 1, wherein an error amount is obtained through the comparing, the error amount comprising at least one of an edge placement error (EPE) and a critical dimension (CD).

5. The manufacturing method of claim 1, wherein generating the 2D contour of the one or more mask pattern elements comprises performing the simulation of manufacturing the one or more mask pattern elements described by the mask process corrected data only with respect to a specific region of the second mask pattern.

6. The manufacturing method of claim 1, further comprising, after verifying the MPC, verifying at a wafer level by inputting data about the 2D contour into an optical proximity correction (OPC) verification tool.

7. The manufacturing method of claim 6, wherein the 2D contour is output only with respect to a specific region of the second mask pattern for a plurality of pattern elements regularly distributed across the second mask pattern, and verifying at the wafer level comprises performing the verification at the wafer level only on the specific region.

8. The manufacturing method of claim 6, further comprising:

determining that the OPC deviates from an allowable range;

in response to determining the OPC deviates from the allowable range, re-performing the MPC to obtain modified mask process corrected data;

verifying that the OPC is within the allowable range based on the re-performed MPC; and

using the modified mask process corrected data to manufacture a mask.

9. The manufacturing method of claim 6, further comprising performing a topology check and a fracture before performing the verification on the MPC.

10. The manufacturing method of claim 1,

wherein the mask process correction performs a transformation of the MTO design data to obtain the mask process corrected data based upon the mask process model.

11. A manufacturing method comprising:

performing a mask process correction (MPC) on mask tape-out (MTO) design data describing a first mask pattern by applying the MPC to the MTO design data to obtain mask process corrected data describing a second mask pattern;

verifying the performance of the MPC by generating a two-dimensional (2D) contour of one or more mask pattern elements by performing a simulation of manufacturing corresponding one or more mask pattern elements described by the mask process corrected data using a mask process model;

manufacturing at least one of a mask and a semiconductor device in response to the verifying, including

generating pixel data based on the mask process corrected data;

performing electron beam writing on a mask blank based on the pixel data; and

forming the mask by performing a development process and an etching process on a mask substrate,

wherein the MPC is responsive to the mask process model and the mask process model is adjustable based on the verifying.

12. The manufacturing method of claim 11, wherein verifying the performance of the MPC comprises:

comparing the 2D contour with a shape described by the MTO design data.

13. The manufacturing method of claim 12, wherein an error amount is obtained through the comparing, the error amount comprising at least one of an edge placement error (EPE) and a critical dimension (CD), and the simulation is performed only with respect to a specific portion of the second mask pattern.

14. The manufacturing method of claim 11, further comprising performing verification at a wafer level by inputting data about the 2D contour into an optical proximity correction (OPC) verification tool after verifying the performance of the MPC.

15. The manufacturing method of claim 14, further comprising:

determining that the OPC is within an allowable range; and

using the mask process corrected data to manufacture at least one of a mask and a semiconductor device.

16. A manufacturing method comprising:

performing a mask process correction (MPC) on mask tape-out (MTO) design data describing a first mask pattern by applying the MPC to the MTO design data to obtain mask process corrected data describing a second mask pattern;

verifying the performance of the MPC by generating a two-dimensional (2D) contour of one or more mask pattern elements by performing a simulation of manufacturing corresponding one or more mask pattern elements described by the mask process corrected data using a mask process model;

manufacturing at least one of a mask and a semiconductor device in response to the verifying, including

wherein the mask tape-out (MTO) design data describes the first mask pattern having a plurality of first mask pattern elements;

wherein performing the MPC comprises obtaining the mask process corrected data by applying the mask process correction to the MTO design data, the mask process corrected data representing a second mask pattern having a plurality of second mask pattern elements, each of the second mask pattern elements corresponding to a respective one of first mask pattern elements, at least some of the second mask pattern elements having a different size than the corresponding first mask pattern element;

wherein verifying the performance of the MPC comprises;

using the mask process model, simulating a manufacture of one or more of the second mask pattern elements to obtain first contours respectively corresponding to the one or more second mask pattern elements;

determining a plurality of first deviation values, by, for each first contour, comparing the first contour to a corresponding first mask pattern element, to obtain a first deviation value for each first contour;

based on the plurality of first deviation values, determining that the mask process correction is insufficient;

adjusting the mask process model;

adjusting the mask process correction based on the adjusted mask process model;

using the adjusted mask process correction, modifying the MTO design data to obtain modified mask process corrected data representing a third mask pattern having a plurality of third mask pattern elements, each of the third mask pattern elements corresponding to a respective one of the first mask pattern elements, at least some of the third mask pattern elements having a different size than the corresponding first mask pattern element;

using the adjusted mask process model, simulating a manufacture of one or more of the third mask pattern elements to obtain corresponding second contours respectively corresponding to the one or more third mask pattern elements;

determining a plurality of second deviation values, by, for each second contour, comparing the second contour to a corresponding first mask pattern element, to obtain a second deviation value for each second contour; and

based on the plurality of second deviation values, determining that the mask process correction is sufficient, and

wherein the manufacturing of at least one of a mask and a semiconductor device uses the modified mask process corrected data.

17. The method of claim 16, wherein determining the plurality of first deviation values comprises, for each first contour, determining deviations of locations of points of edges of the first contour with locations of corresponding points of edges of the corresponding first mask pattern element.

18. The method of claim 17,

wherein determining deviations of locations comprises determining deviations with respect to locations of first points of first edges of the first contour located at one or more of extremities of the first contour, corners of the first contour and edges having a radius of curvature below a predetermined value, and with respect to second points of second edges of the first contour,

wherein the second points are spaced apart from each other further than the first points are spaced apart from each other.

19. The method of claim 16, wherein the manufacturing of at least one of a mask and a semiconductor device is performed with process parameters described by the adjusted mask process model.

20. The method of claim 16, further comprising verifying an optical proximity correction mask element by simulating a photolithography process using the first contours.