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Non-volatile memory device

  • US 10,224,098 B2
  • Filed: 03/28/2018
  • Issued: 03/05/2019
  • Est. Priority Date: 09/30/2005
  • Status: Active Grant
First Claim
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1. A non-volatile memory device comprising:

  • a plurality of memory blocks, each memory block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells;

    a clock port configured to receive a clock signal;

    a control port configured to receive a chip select signal,at least one common data interface configured to transfer command data, address data, input data and output data only when the chip select signal is at an active low logic state, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the non-volatile memory device is in a double data rate implementation;

    a control circuitry configured to perform a program operation to program the input data on a selected page according to the command data and address data, and to perform a read operation to retrieve the output data from a different page other than the selected page before completion of the program operation; and

    a status register configured to indicate a status of the program operation.

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