Non-volatile memory device
First Claim
1. A non-volatile memory device comprising:
- a plurality of memory blocks, each memory block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells;
a clock port configured to receive a clock signal;
a control port configured to receive a chip select signal,at least one common data interface configured to transfer command data, address data, input data and output data only when the chip select signal is at an active low logic state, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the non-volatile memory device is in a double data rate implementation;
a control circuitry configured to perform a program operation to program the input data on a selected page according to the command data and address data, and to perform a read operation to retrieve the output data from a different page other than the selected page before completion of the program operation; and
a status register configured to indicate a status of the program operation.
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Accused Products
Abstract
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
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Citations
18 Claims
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1. A non-volatile memory device comprising:
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a plurality of memory blocks, each memory block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells; a clock port configured to receive a clock signal; a control port configured to receive a chip select signal, at least one common data interface configured to transfer command data, address data, input data and output data only when the chip select signal is at an active low logic state, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the non-volatile memory device is in a double data rate implementation; a control circuitry configured to perform a program operation to program the input data on a selected page according to the command data and address data, and to perform a read operation to retrieve the output data from a different page other than the selected page before completion of the program operation; and a status register configured to indicate a status of the program operation. - View Dependent Claims (2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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5. The non-volatile memory device as claimed in 1, wherein the status register is configured to provide a result of the program operation after the program operation is completed.
Specification