Non-volatile memory device

• US 10,224,098 B2
• Filed: 03/28/2018
• Issued: 03/05/2019
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): Audong, Gene
• Application Number:
  US15/937,937
• Publication Number:
  US 20180261282A1
• Time in Patent Office: 342 Days
• Field of Search: 365221, 36518511, 36518529, 36518905, 36518512, 36518915, 3652331, 365239
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A non-volatile memory device comprising:

a plurality of memory blocks, each memory block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells;

a clock port configured to receive a clock signal;

a control port configured to receive a chip select signal,

at least one common data interface configured to transfer command data, address data, input data and output data only when the chip select signal is at an active low logic state, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the non-volatile memory device is in a double data rate implementation;

a control circuitry configured to perform a program operation to program the input data on a selected page according to the command data and address data, and to perform a read operation to retrieve the output data from a different page other than the selected page before completion of the program operation; and

a status register configured to indicate a status of the program operation.

2. The non-volatile memory device as claimed in claim 1, further comprising a clock output port configured to transmit a clock output signal in synchronization with the output data.

3. The non-volatile memory device as claimed in claim 1, wherein the control circuitry is configured to perform an erase operation to erase a selected memory block, and to perform a second read operation to retrieve a second output data from a different memory block other than the selected memory block before completion of the erase operation.

4. The non-volatile memory device as claimed in claim 3, wherein the status register is configured to indicate a status of the erase operation.

6. The non-volatile memory device as claimed in claim 3, wherein the status register is configured to provide a result of the erase operation after the erase operation is completed.

7. The non-volatile memory device as claimed in claim 1, wherein the at least one of command data, address data, input data and output data is transferred in synchronization with one of rising and falling edges of the clock signal when the non-volatile memory device is in a single data rate implementation.

8. The non-volatile memory device as claimed in claim 1, wherein a transition of the chip select signal from the active low logic state to an inactive high logic state indicates an end of the transfer of the at least one of command data, address data, input data and output data.

9. The non-volatile memory device as claimed in claim 1, further comprising a second control port configured to receive a reset signal to reset the program operation.

10. The non-volatile memory device as claimed in claim 1, further comprising an error correcting code (ECC) configured to be utilized during the program operation.

11. The non-volatile memory device as claimed in claim 1, wherein the control circuitry is configured to automate the program operation including program pulse repetition and an internal verification operation.

12. The non-volatile memory device as claimed in claim 3, wherein the control circuitry is configured to automate the erase operation including erase pulse repetition and an internal verification operation.

13. The non-volatile memory device as claimed in claim 1, wherein the each page includes a data field and a spare field.

14. The non-volatile memory device as claimed in claim 1, wherein the at least one common data interface comprises a serial input port and a serial output port.

15. The non-volatile memory device as claimed in claim 1, wherein the non-volatile memory device is a NAND flash memory device.

16. The non-volatile memory device as claimed in claim 1, wherein the non-volatile memory device is a NOR flash memory device.

17. The non-volatile memory device as claimed in claim 1, wherein the at least one common data interface comprises a single-bit serial data interface.

18. The non-volatile memory device as claimed in claim 1, wherein the at least one common data interface comprises a multi-bit serial data interface.

5. The non-volatile memory device as claimed in 1, wherein the status register is configured to provide a result of the program operation after the program operation is completed.