Non-volatile memory

• US 10,224,108 B2
• Filed: 01/03/2018
• Issued: 03/05/2019
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Ching, Wen-Hao, Wang, Shih-Chen
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US15/860,786
• Publication Number:
  US 20180197872A1
• Time in Patent Office: 426 Days
• Field of Search: 36518518, 36518505, 36518529, 36518508, 36518503, 36518513, 36518521, 36518526, 365149, 36518514, 36518519, 36518909, 365145, 365175, 36518525, 3651852, 365203, 36518511, 36518517
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H03K 17/0828 in composite switches
• CPC Class Codes: H03K 19/088 Transistor-transistor logic
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Claims

1. A non-volatile memory comprising a first memory cell, the first memory cell comprising:

a first transistor comprising a first gate, a first terminal and a second terminal;

a second transistor comprising a second gate, a third terminal and a fourth terminal;

a third transistor comprising a third gate, a fifth terminal and a sixth terminal;

a fourth transistor comprising a fourth gate, a seventh terminal and an eighth terminal;

a fifth transistor comprising a fifth gate, a ninth terminal and a tenth terminal; and

a first capacitor connected between the third gate and a control line,

wherein the third gate is a floating gate, the second terminal is connected with the third terminal, the fourth terminal is connected with the fifth terminal, the sixth terminal is connected with the seventh terminal, and the eighth terminal is connected with the ninth terminal; and

wherein the first terminal is connected with a first bit line, the tenth terminal is connected with a first source line, the first gate is connected with a first word line, the second gate is connected with a first auxiliary line, the fourth gate is connected with a second auxiliary line, and the fifth gate is connected with a second word line.

2. The non-volatile memory as claimed in claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are n-type transistors.

3. The non-volatile memory as claimed in claim 1, wherein the first memory cell further comprises a second capacitor, and the second capacitor is connected with the third gate and an erase line.

4. The non-volatile memory as claimed in claim 3, wherein the first capacitor is composed of a sixth transistor, and the second capacitor is composed of a seventh transistor, wherein the sixth transistor comprises a sixth gate, an eleventh terminal and a twelfth terminal, and the seventh transistor comprises a seventh gate, a thirteenth terminal and a fourteenth terminal, wherein both of the sixth gate and the seventh gate are connected with the third gate, both of the eleventh terminal and the twelfth terminal are connected with the control line, and both of the thirteenth terminal and the fourteenth terminal are connected with the erase line.

5. The non-volatile memory as claimed in claim 4, wherein a gate oxide layer in each of the third transistor, the sixth transistor and the seventh transistor has a first thickness.

6. The non-volatile memory as claimed in claim 5, wherein a gate oxide layer in each of the first transistor and the fifth transistor has a second thickness, a gate oxide layer in each of the second transistor and the fourth transistor has the first thickness, wherein the first thickness is larger than the second thickness.

7. The non-volatile memory as claimed in claim 3, wherein when a program action is performed, a program voltage is provided to the control line and the erase line, a first voltage is provided to the second word line, a second voltage is provided to the second auxiliary line, a third voltage is provided to the first word line, a fourth voltage is provided to the first auxiliary line, and a ground voltage is provided to the bit line and the source line, wherein the program voltage is higher than the second voltage, the second voltage is equal to the fourth voltage, the first voltage is equal to the third voltage, the second voltage is higher than or equal to the first voltage, and the first voltage is higher than the ground voltage.

8. The non-volatile memory as claimed in claim 3, wherein when a program inhibition is performed, a program voltage is provided to the control line and the erase line, a first voltage is provided to the second word line, a second voltage is provided to the second auxiliary line, a third voltage is provided to the first word line, a fourth voltage is provided to the first auxiliary line, a fifth voltage is provided to the bit line, and a sixth voltage is provided to the source line, wherein the program voltage is higher than the second voltage, the second voltage is equal to the fourth voltage, the first voltage is equal to the third voltage, the fifth voltage is equal to the sixth voltage, the second voltage is higher than or equal to the first voltage, and the first voltage is higher than or equal to the fifth voltage.

9. The non-volatile memory as claimed in claim 3, wherein when an erase action is performed, an erase voltage is provided to the erase line, a first voltage is provided to the second word line, a second voltage is provided to the second auxiliary line, a third voltage is provided to the first word line, a fourth voltage is provided to the first auxiliary line, and a ground voltage is provided to the control line, the bit line and the source, wherein the erase voltage is higher than the second voltage, the second voltage is equal to the fourth voltage, the first voltage is equal to the third voltage, the second voltage is higher than or equal to the first voltage, and the first voltage is higher than the ground voltage.

10. The non-volatile memory as claimed in claim 3, wherein when a read action is performed, a read voltage is provided to the bit line, a first voltage is provided to the second word line, a second voltage is provided to the second auxiliary line, a third voltage is provided to the first word line, a fourth voltage is provided to the first auxiliary line, a fifth voltage is provided to the control line, a sixth voltage is provided to the erase line, and a ground voltage is provided to the source line, wherein the second voltage is equal to the fourth voltage, the first voltage is equal to the third voltage, the fifth voltage is equal to the sixth voltage, the second voltage is higher than or equal to the first voltage, the fifth voltage is higher than or equal to the ground voltage, and the read voltage is higher than the ground voltage.

11. A non-volatile memory, comprising:

a first word line;

a second word line;

a first auxiliary line;

a second auxiliary line;

a first control line;

a first erase line;

a first bit line;

a first source line; and

a first memory cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the first transistor comprises a first gate, a first terminal and a second terminal, the second transistor includes a second gate, a third terminal and a fourth terminal, the third transistor comprises a third gate, a fifth terminal and a sixth terminal, the fourth transistor comprises a fourth gate, a seventh terminal and an eighth terminal, the fifth transistor comprises a fifth gate, a ninth terminal and a tenth terminal, the first capacitor is connected between the third gate and the control line, and the second capacitor is connected with the third gate and the first erase line;

wherein the third gate is a floating gate, the second terminal is connected with the third terminal, the fourth terminal is connected with the fifth terminal, the sixth terminal is connected with the seventh terminal, the eighth terminal is connected with the ninth terminal, the first terminal is connected with the first bit line, the tenth terminal is connected with the first source line, the first gate is connected with the first word line, the second gate is connected with the first auxiliary line, the fourth gate is connected with the second auxiliary line, and the fifth gate is connected with the second word line.

12. The non-volatile memory as claimed in claim 11, further comprising:

a second bit line;

a second source line; and

a second memory cell comprising a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third capacitor and a fourth capacitor, wherein the sixth transistor comprises a sixth gate, an eleventh terminal and a twelfth terminal, the seventh transistor includes a seventh gate, a thirteenth terminal and a fourteenth terminal, the eighth transistor comprises an eighth gate, a fifteenth terminal and a sixteenth terminal, the ninth transistor comprises a ninth gate, a seventeenth terminal and an eighteenth terminal, the tenth transistor comprises a tenth gate, a nineteenth terminal and a twentieth terminal, the third capacitor is connected between the eighth gate and the first control line, and the fourth capacitor is connected with the eighth gate and the first erase line,

wherein the eighth gate is a floating gate, the twelfth terminal is connected with the thirteenth terminal, the fourteenth terminal is connected with the fifteenth terminal, the sixteenth terminal is connected with the seventeenth terminal, the eighteenth terminal is connected with the nineteenth terminal, the eleventh terminal is connected with the second bit line, the twentieth terminal is connected with the second source line, the sixth gate is connected with the first word line, the seventh gate is connected with the first auxiliary line, the ninth gate is connected with the second auxiliary line, and the tenth gate is connected with the second word line.

13. The non-volatile memory as claimed in claim 12, wherein the first word line and the second word line are connected with each other, and the first auxiliary line and the second auxiliary line are connected with each other.

14. The non-volatile memory as claimed in claim 12, further comprising:

a third word line;

a fourth word line;

a third auxiliary line;

a fourth auxiliary line;

a second control line;

a second erase line; and

a third memory cell comprising an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a fifth capacitor and a sixth capacitor, wherein the eleventh transistor comprises an eleventh gate, a twenty-first terminal and a twenty-second terminal, the twelfth transistor includes a twelfth gate, a twenty-third terminal and a twenty-fourth terminal, the thirteenth transistor comprises a thirteenth gate, a twenty-fifth terminal and a twenty-sixth terminal, the fourteenth transistor comprises a fourteenth gate, a twenty-seventh terminal and a twenty-eighth terminal, the fifteenth transistor comprises a fifteenth gate, a twenty-ninth terminal and a thirtieth terminal, the fifth capacitor is connected between the thirteenth gate and the second control line, and the sixth capacitor is connected with the thirteenth gate and the second erase line,

wherein the thirteenth gate is a floating gate, the twenty-second terminal is connected with the twenty-third terminal, the twenty-fourth terminal is connected with the twenty-fifth terminal, the twenty-sixth terminal is connected with the twenty-seventh terminal, the twenty-eighth terminal is connected with the twenty-ninth terminal, the twenty-first terminal is connected with the first bit line, the thirtieth terminal is connected with the first source line, the eleventh gate is connected with the third word line, the twelfth gate is connected with the third auxiliary line, the fourteenth gate is connected with the fourth auxiliary line, and the fifteenth gate is connected with the fourth word line.

15. The non-volatile memory as claimed in claim 12, wherein the third word line and the fourth word line are connected with each other, and the third auxiliary line and the fourth auxiliary line are connected with each other.