Semiconductor device using a parallel bit operation and method of operating the same

• US 10,224,114 B2
• Filed: 05/20/2017
• Issued: 03/05/2019
• Est. Priority Date: 06/02/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ryu, Je-min, Yu, Hak-soo, Oh, Reum, Seo, Seong-young, Rho, Soo-jung
• Primary Examiner(s): Alrobaie, Khamdan N.
• Application Number:
  US15/600,715
• Publication Number:
  US 20170352434A1
• Time in Patent Office: 654 Days
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

Claims

1. A memory device comprising:

a memory cell array comprising a plurality of memory cells; and

an internal operation circuit configured to perform both a test operation and an internal operation using a parallel bit operation of simultaneously comparing a plurality of bits,

wherein the internal operation circuit is configured to perform the test operation in a test mode of the memory device and the internal operation in an internal operation mode other than the test mode of the memory device based on a command signal received from an outside of the memory device, and

wherein the internal operation circuit comprises;

a mode selector configured to provide comparison data received from a host to a parallel bit comparator,

wherein the parallel bit comparator is configured to compare read data from the memory cell array with the comparison data to find second data corresponding to the comparison data, and to compare an address of valid data indicated by the second data with an address of the second data to output a result of the comparison to a result generator, and

wherein the result generator is configured to output the comparison result obtained by the parallel hit comparator.

2. The memory device of claim 1, wherein the

mode selector is configured to set a mode of the internal operation circuit as the test mode or the internal operation mode, and

wherein the parallel bit comparator is configured to perform a parallel bit comparison (PBC) between data read out from the memory cell array and the comparison data using the parallel bit operation.

3. The memory device of claim 2, wherein the mode selector comprises a pattern analyzer configured to set the mode of the internal operation circuit as the internal operation mode based on the command signal including data or an address that is received from an outside of the memory device.

4. The memory device of claim 2, wherein the memory device includes a control logic circuit configured to control the memory device, and

wherein the mode selector is configured to set the mode of the internal operation circuit as the internal operation mode according to a signal received from an external pin or a command signal received from the control logic circuit.

5. The memory device of claim 1, wherein the

parallel bit comparator is configured to perform a comparison operation of comparing read data from the memory cell array with the comparison data and searching for first data matched with the comparison data from the memory cell array.

6. The memory device of claim 5, wherein, when the parallel bit comparator finds the first data, the result generator is configured to output a hit signal to the host, and when the parallel bit comparator does not find the first data, the result generator is configured to output a miss signal to the host.

7. The memory device of claim 5, wherein the parallel bit comparator is configured to control a fine comparison operation of comparing the comparison data with the read data in units of bits or bytes and outputting a result of the comparison.

8. The memory device of claim 5, wherein the parallel bit comparator is configured to perform a fine comparison operation of comparing the comparison data with the read data in units of bits or bytes and combining and outputting results of the fine comparisons.

9. The memory device of claim 5, further comprising:

a control logic circuit configured to control the memory device,

wherein the control logic circuit is configured to perform a data processing operation according to the internal operation by using at least one of the first data and an address corresponding to the first data.

10. The memory device of claim 9, wherein the internal operation circuit is configured to perform the internal operation by the control logic circuit by changing a format of the first data and rewriting the changed format of the first data to an address corresponding to the first data.

11. The memory device of claim 9, wherein:

the memory device is configured to receive one or more target addresses from an external source, and

the internal operation circuit is configured to perform, as the internal operation by the control logic circuit, at least one of;

a copy operation of copying the first data to memory cells corresponding to a first target address;

a move operation of moving the first data to memory cells corresponding to a second target address; and

a swap operation of swapping the first data with second data stored in memory cells corresponding to a third target address.

12. The memory device of claim 11, wherein:

the memory cell array comprises a first area and a second area that is more frequently accessed by the host than the first area, and

the one or more target addresses corresponds to the second area.

13. A semiconductor device comprising:

an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits, and to perform an internal operation comprising a comparison operation with respect to external data in a normal mode other than the test mode by using the parallel bit operation,

wherein the internal operation circuit comprises;

a mode selector configured to set a mode of the internal operation circuit as the test mode or an internal operation mode of the normal mode;

a parallel bit comparator configured to perform a parallel bit comparison (PBC) between data read out from a memory cell array and the external data received from an outside of the semiconductor device by using the parallel bit operation; and

a result generator configured to output a comparison result obtained by the parallel bit comparator,

wherein, in the internal operation, the internal operation circuit is configured to find the external data from the memory cell array by using the parallel bit operation, and wherein;

the semiconductor device is configured to read data from a memory cell array within or outside the semiconductor device, and

the internal operation circuit is configured to perform, as the internal operation, at least one of;

a search operation of comparing the data read out from the memory cell array with comparison data received from a memory controller to find first data identical to the comparison data and outputting a hit signal to a host when the first data is found;

a copy operation of receiving a first target address from the memory controller and copying the first data to memory cells of the memory cell array corresponding to the first target address;

a move operation of receiving a second target address from the memory controller and moving the first data to memory cells of the memory cell array corresponding to the second target address; and

a swap operation of receiving a third target address from the memory controller and swapping the first data with second data stored in memory cells of the memory cell array corresponding to the third target address.

14. A memory device comprising:

a memory cell array comprising a plurality of memory cells; and

an internal operation circuit including a parallel bit comparator configured to simultaneously compare first data from a first set of memory cells of the memory cell array with second data received from outside the memory device in an internal operation mode of the memory device,

wherein the parallel bit comparator is configured to operate in a test mode of the memory device for a parallel bit operation,

wherein, in the internal operation mode, the internal operation circuit is configured to find the second data from the memory cell array by using the parallel bit operation,

wherein the internal operation circuit is configured to perform at least one of;

a rewrite operation of rewriting the second data in the first set of memory cells of the memory cell array corresponding to a first address,

a copy operation of copying the first data to a second set of memory cells of the memory cell array corresponding to a second address,

a move operation of moving the first data to a third set of memory cells of the memory cell array corresponding to a third address, and

a swap operation of swapping the first data with a third data stored in a fourth set of memory cells of the memory cell array corresponding to a fourth address.

15. The memory device of claim 14, wherein the internal operation circuit is configured to, when the memory device operates in the internal operation mode, provide an output signal to either an internal circuit of the memory device or an outside of the memory device, and

wherein the output signal of the internal operation circuit includes first data and a first address signal.

16. The memory device of claim 15, wherein the internal circuit of the memory device includes an address buffer and a data buffer both connected to the internal operation circuit, and

wherein the data buffer is configured to write the first data to the memory cell array, and the address buffer is configured to receive the first address signal in the internal operation mode.

17. The memory device of claim 14, wherein the internal operation circuit includes a mode selector configured to receive a command signal from either an internal control logic circuit of the memory device or an outside of the memory device, and to output a test mode instruction signal such that the memory device performs the parallel bit operation and an internal operation mode instruction signal such that the memory device performs an internal operation based on the received command signal.