Mechanical suppression of parasitic plasma in substrate processing chamber

• US 10,224,182 B2
• Filed: 11/23/2011
• Issued: 03/05/2019
• Est. Priority Date: 10/17/2011
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Keil, Douglas, Augustyniak, Edward, Leeser, Karl, Sabri, Mohamed
• Primary Examiner(s): Baldwin, Gordon
• Assistant Examiner(s): Javed, Mirza Israr
• Application Number:
  US13/303,386
• Publication Number:
  US 20130092086A1
• Time in Patent Office: 2,659 Days
• Field of Search: 118156, 118728-730, 118723 E, 15634551-34555, 15634543-34547, 361234
• CPC Class Codes: C23C 16/45565 Shower nozzles
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01J 37/32495 Means for protecting the vessel against plasma
• CPC Class Codes: H01J 37/3255 Material
• CPC Class Codes: H01J 37/32623 Mechanical discharge control means

Abstract

A system for reducing parasitic plasma in a semiconductor process comprises a first surface and a plurality of dielectric layers that are arranged between an electrode and the first surface. The first surface and the electrode have substantially different electrical potentials. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.

Claims

1. A system for reducing parasitic plasma in a semiconductor process, comprising:

a first surface of a conducting structure; and

a plurality of dielectric layers that are vertically stacked between an electrode and the first surface,

wherein the first surface and the electrode have substantially different electrical potentials,

wherein the plurality of dielectric layers defines;

a first gap between the electrode and one of the plurality of dielectric layers,

a second gap between adjacent ones of the plurality of dielectric layers, and

a third gap between a last one of the plurality of dielectric layers and the first surface, and

wherein a number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.

2. The system of claim 1, wherein the conducting structure corresponds to a grounded conducting structure.

3. The system of claim 1, further comprising barriers arranged between radially outer ends of the plurality of dielectric layers to prevent incursion of deposition precursor species between the plurality of dielectric layers.

4. The system of claim 1, wherein diameters of each of the plurality of dielectric layers decrease as a distance increases between the electrode and a respective one of the plurality of dielectric layers.

5. The system of claim 1, wherein each of the plurality of dielectric layers comprises a radially inner portion having a first thickness in an axial direction and a protruding portion that extends radially outwardly and has a second thickness in the axial direction.

6. The system of claim 5, wherein a difference between the first thickness and the second thickness is equal to the second gap.

7. The system of claim 1, wherein the semiconductor process comprises plasma-enhanced chemical vapor deposition (PECVD).

8. A pedestal system comprising:

the system of claim 2; and

a pedestal platen that supports a substrate and that is made of a non-conducting material,

the electrode, wherein the electrode is embedded in the pedestal platen.

9. The pedestal system of claim 8, wherein during the semiconductor process, the grounded conducting structure is connected to RF ground and the electrode is connected to an RF bias.

10. The pedestal system of claim 8, further comprising:

a collar that is connected to the first surface; and

an adapter that is connected to the collar.

11. The pedestal system of claim 10, wherein the first surface, the collar and the adapter are made of aluminum.

12. The pedestal system of claim 8, wherein the pedestal platen comprises ceramic, the first surface comprises a conducting disk, the electrode comprises wire mesh and each of the plurality of dielectric layers comprises a disk.

13. A pedestal system for a semiconductor process, comprising:

a pedestal platen that supports a substrate, that is made of a non-conducting material and that includes an electrode embedded therein;

a first surface of a conducting structure having a substantially different electrical potential than the electrode;

N dielectric layers that are vertically stacked between the pedestal platen and the first surface, where N is an integer that is greater than one; and

wherein the N dielectric layers define;

a first gap between the pedestal platen and the N dielectric layers,

a second gap between adjacent ones of the N dielectric layers, and

a third gap between the N dielectric layers and the first surface, and

wherein N and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.

14. The pedestal system of claim 13, wherein the electrode is connected to an RF bias and the first surface is connected to RF ground during the semiconductor process.

15. The pedestal system of claim 13, further comprising:

a collar that is connected to the first surface; and

an adapter that is connected to the collar.

16. The pedestal system of claim 15, wherein the first surface, the collar and the adapter are made of aluminum.

17. The pedestal system of claim 13, wherein the pedestal platen comprises ceramic and wherein the electrode comprises wire mesh.

18. The pedestal system of claim 13, wherein N and a width of the second gap are selected to prevent plasma formation between the N dielectric layers.

19. The pedestal system of claim 13, wherein the N dielectric layers comprise a radially inner portion having a first thickness in an axial direction and a protruding portion that extends radially outwardly and has a second thickness in the axial direction, and wherein a difference between the first thickness and the second thickness is equal to the second gap.

20. The pedestal system of claim 13, wherein the pedestal platen has a diameter that is greater than a diameter of the N dielectric layers, and wherein the N dielectric layers have a diameter that is greater than the first surface.

21. The pedestal system of claim 13, further comprising barriers arranged between radially outer ends of the N dielectric layers.