Electronic devices and systems, and methods for making and using the same

• US 10,224,244 B2
• Filed: 08/19/2016
• Issued: 03/05/2019
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Thompson, Scott E., Thummalapally, Damodar R.
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US15/241,337
• Publication Number:
  US 20160358918A1
• Time in Patent Office: 928 Days
• Field of Search: 257192, 257213, 257288, 257304, 257322, 257396, 257347, 257351, 257E21006, 257E21042, 257E21051, 257E21267, 257E2132, 257E214, 257E21435, 257E21545
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV_T compared to conventional bulk CMOS and can allow the threshold voltage V_T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Claims

1. A semiconductor device, comprising:

a first CMOS circuit and a second CMOS circuit comprising deeply depleted channel (DDC) field effect transistors (FETs);

each of the DDC FETs having a well with a first conductive type, a screening region with the first conductive type on the well, an un-doped channel layer above the screening region, a threshold voltage tuning region with the first conductive type positioned between the un-doped channel layer and the screening region to modify a threshold voltage of the DDC FETs, a gate stack positioned above the un-doped channel layer to control conduction between a drain and source positioned at both sides of the gate stack;

wherein a dopant concentration of the threshold voltage tuning region is lower than a dopant concentration of the screening region;

wherein there is not a local minimum between the threshold voltage tuning region and the screening region in a depth profile of the first type of dopant;

wherein the screening region sets a depth of a depletion layer below the gate stack in a direction from the un-doped channel layer toward the screening region; and

wherein the well of the first CMOS circuit is applied with a first body bias voltage and the well of the second CMOS circuit is applied with a second body bias voltage different from the first body bias voltage.

2. The semiconductor device of claim 1, wherein the first mode or the second mode is set statically.

3. The semiconductor device of claim 1, further comprising:

a punch through suppression region with the first conductive type positioned between the screening region and the well, a dopant concentration of the punch through suppression region are lower than a dopant concentration of the screening region.

4. The semiconductor device of claim 1, wherein the depletion layer does not go through the screening region, regardless of the first body bias voltage and the second body bias voltage when a voltage of the gate stack equals to the threshold voltage.

5. The semiconductor device of claim 1, wherein the first mode or the second mode is set dynamically.

6. The semiconductor device of claim 5, wherein the mode is set statically.

7. The semiconductor device of claim 5, wherein the mode is set dynamically.

8. A semiconductor device comprising a first circuit block and a second circuit block:

a first circuit block comprising a first field effect transistor;

the first field effect transistor comprising;

a first doped well being doped with a first type of dopant and having a first dopant concentration;

a first gate positioned above the first doped well to control conduction between a first drain and a first source;

a first undoped channel having a second dopant concentration of less than 5×

10¹⁷ atoms/cm³, the first undoped channel being situated between the first drain and the first source and below the first gate;

a first screening region being doped with the first type of dopant and having a third dopant concentration greater than ten times the second dopant concentration and greater than the first dopant concentration the first screening region positioned on the first doped well;

a first threshold voltage tuning region positioned between the first undoped channel and the first screening region to modify a threshold voltage of the first field effect transistor, the first threshold voltage tuning region being doped with the first type of dopant and having a fourth dopant concentration less than the third dopant concentration; and

a first body tap electrically coupled to the first doped well such that the first doped well is supplied with a first body bias voltage,

a second circuit block comprising a second field effect transistor;

the second field effect transistor comprising;

a second doped well being doped with a second type of dopant and having a fifth dopant concentration;

a second gate positioned above the second doped well to control conduction between a second drain and a second source;

a second undoped channel having a sixth dopant concentration of less than 5×

10¹⁷ atoms/cm, the second undoped channel being situated between the second drain and the source and below the second gate;

a second screening region being doped with the second type of dopant and having a seventh dopant concentration greater than ten times the sixth dopant concentration and greater than the fifth dopant concentration, the second screening region positioned on the second doped well;

a second threshold voltage tuning region positioned between the second undoped channel and the second screening region to modify a threshold voltage of the second field effect transistor, the threshold voltage tuning region being doped with the second type of dopant and having an eighth dopant concentration less than the seventh dopant concentration,

a second body tap electrically coupled to the second doped well such that the second doped well is supplied with a second body bias voltage,

wherein the first doped well is isolated from the second doped well, the first body bias voltage is supplied independently from the second body bias voltage, and the first circuit block operates at a first mode different from a second mode at which the second circuit block operates;

wherein the first screening region sets a depth of a depletion layer below the first gate stack in a direction from the first un-doped channel layer toward the first screening region; and

wherein there is not a local minimum between the first threshold voltage tuning region and the first screening region in a depth profile of the first type of dopant.

9. The semiconductor device of claim 8, wherein

the first field effect transistor further comprising a first punch through suppression region positioned between the first screening region and the first doped well, the first punch through suppression region being doped with the first type of dopant and having a fifth dopant concentration :

less than the third dopant concentration; and

the second field effect transistor comprising a second punch through suppression region positioned between the second screening region and the second doped well, the second punch through suppression region being doped with the second type of dopant and having a ninth dopant concentration less than the seventh dopant concentration.

10. A semiconductor device comprising a plurality of circuit blocks:

each of the circuit blocks comprising a field effect transistor;

the field effect transistor comprising;

a doped well being doped with a first type of dopant and having a first dopant concentration;

a gate positioned above the doped well to control conduction between a drain and source;

an undoped channel having a second dopant concentration of less than 5×

10¹⁷ atoms/cm³, the undoped channel being situated between the drain and the source and below the gate;

a screening region being doped with the first type of dopant and having a third dopant concentration greater than ten times the second dopant concentration and greater than the first dopant concentration, the screening region positioned on the doped well;

a threshold voltage tuning region positioned between the =doped channel and the screening region to modify a threshold voltage of the field effect transistor, the threshold voltage tuning region being doped with the first type of dopant and having a fourth dopant concentration less than the third dopant concentration;

a body tap electrically coupled to the doped well such that the doped well is supplied with a body bias voltage,

wherein the screening region sets a depth of a depletion layer below the gate stack in a direction from the un-doped channel layer toward the screening region;

wherein there is not a local minimum between the threshold voltage tuning region and the screening region in a depth profile of the first type of dopant; and

wherein each of the circuit blocks has the doped well isolated from other circuit blocks, each of the body bias voltage of the plurality of circuit blocks is independent to each other, and each of the circuit blocks operates at a mode different from each other.

11. The semiconductor device of claim 10, further comprising:

a punch through suppression region positioned between the screening region and the doped well, the punch through suppression region being doped with the first type of dopant and having a fifth dopant concentration less than the third dopant concentration.

12. A semiconductor device, comprising:

a first CMOS circuit and a second CMOS circuit comprising deeply depleted channel (DDC) field effect transistors (FETs);

each of the DDC FETs having a well with a first conductive type, a screening region with the first conductive type being electrically coupled to the well, an un-doped channel layer above the screening region, a threshold voltage tuning region with the first conductive type positioned between the un-doped channel layer and the screening region to modify the threshold voltage of the DDC FETs, a gate stack positioned above the un-doped channel layer to control conduction between a drain and source positioned at both sides of the gate stack;

wherein a dopant concentration of the threshold voltage tuning region is lower than a dopant concentration of the screening region;

wherein the well of the first CMOS circuit is applied with a first body bias voltage and the well of the second CMOS circuit is applied with a second body bias voltage different from the first body bias voltage; and

wherein the screening region separates from the drain and the source.