Semiconductor structure and fabricating method thereof

• US 10,224,248 B2
• Filed: 10/04/2016
• Issued: 03/05/2019
• Est. Priority Date: 10/22/2015
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US15/284,839
• Publication Number:
  US 20170117188A1
• Time in Patent Office: 882 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

In various embodiments of the disclosed subject matter, a semiconductor structure, and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: providing a substrate; implanting first punch-through preventing ions into an NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into a PMOS region of the substrate to form a second implantation layer; etching the substrate to form first fin portions in the NMOS region, and second fin portions in the PMOS region, the remaining first implantation layer forms a first punch-through preventing layer, the remaining second implantation layer forms a second punch-through preventing layer; forming insulating structures between adjacent first fin portions and second fin portions; and performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a substrate including an NMOS region and a PMOS region that are adjacent to each other;

implanting first punch-through preventing ions into the NMOS region of the substrate to form a first implantation layer;

implanting second punch-through preventing ions into the PMOS region of the substrate to form a second implantation layer;

etching the substrate to form a plurality of fin portions, including first fin portions in the NMOS region, and second fin portions in the PMOS region, wherein;

surfaces of the substrate between the first fin portions in the NMOS region are lower than the first implantation layer,

the remaining first implantation layer in the first fin portions that is not etched forms a first punch-through preventing layer,

surfaces of the substrate between the second fin portions in the PMOS region are lower than the second implantation layer, and

the remaining second implantation layer in the second fin portions that is not etched forms a second punch-through preventing layer;

forming insulating structures between adjacent first fin portions and second fin portions, wherein surfaces of the insulating structures are higher than top surfaces of the first punch-through preventing layer and the second punch-through preventing layer;

implanting diffusion preventing ions into insulating structure in the NMOS region after forming the insulating structure; and

performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer after implanting diffusion preventing ions into insulating structure in the NMOS region.

2. The method of claim 1, wherein:

the first punch-through preventing ions are P-type ions including fluoride ions, or boron difluoride; and

the second punch-through preventing ions are N-type ions including arsenic ions.

3. The method of claim 1, wherein:

after performing the annealing process, a doping concentration of the first punch-through preventing ions in the first punch-through preventing layer is in a range from 1.0E18 atom/cm³ to 5.0E19 atom/cm³, and a doping concentration of the second punch-through preventing ions in the second punch-through preventing layer is in a range from 1.0E18 atom/cm³ to 5.0E19 atom/cm³.

4. The method of claim 1, further comprising:

after performing the annealing process, forming a first threshold voltage adjusting layer in the first fin portions, and a second threshold voltage adjusting layer in the second fin portions;

wherein the first threshold voltage adjusting layer is located just above the first punch-through preventing layer, the second threshold voltage adjusting layer is located just above the second punch-through preventing layer.

5. The method of claim 1, further comprising:

making the diffusion preventing ions enter the first punch-through preventing layer to prevent a diffusion of the first punch-through preventing ions;

wherein after performing the annealing process, a doping concentration of the diffusion ions in the first punch-through preventing layer is in a range from 1.0E19 atom/cm³ to 5.0E20 atom/cm³.

6. The method of claim 5, wherein the diffusion preventing ions include carbon ions and nitrogen ions, and are implanted into insulating structure in the NMOS region by using a composite ions implantation process.

7. The method of claim 5, wherein the diffusion preventing ions are implanted into insulating structure in the NMOS region by using a lateral straggle ion implantation process.

8. The method of claim 1, wherein forming the insulating structure comprises:

forming an insulating material layer, a top surface of the insulating layer is non-lower than the top surfaces of the fin portions; and

etching the insulating material layer to make the top surface of the insulating layer lower than the top surfaces of the fin portions to form the insulating structure.

9. The method of claim 8, wherein:

the insulating material layer is formed by using a flowable chemical vapor deposition process, including;

forming a precursor layer, a surface of the precursor layer is non-lower than the top surfaces of the fin portions; and

curing the precursor layer to form the insulating material layer by using a low-temperature annealing process, wherein a temperature of the low-temperature annealing process is in a range from 500°

C. to 600°

C., a duration time of the low-temperature annealing process is in a range from 20 minutes to 40 minutes.

10. A method for forming a semiconductor structure, comprising:

providing a substrate including an NMOS region and a PMOS region that are adjacent to each other;

implanting first punch-through preventing ions into the NMOS region of the substrate to form a first implantation layer;

etching the substrate to form a plurality of fin portions, including first fin portions in the NMOS region, and second fin portions in the PMOS region, wherein;

surfaces of the substrate between the first fin portions in the NMOS region are lower than the first implantation layer, and

the remaining first implantation layer in the first fin portions that is not etched forms a first punch-through preventing layer;

forming insulating structures between adjacent first fin portions and second fin portions, wherein surfaces of the insulating structure are higher than top surfaces of the first punch-through preventing layer;

after forming the insulating structures, implanting second punch-through preventing ions into the PMOS region of the substrate, and making the second punch-through preventing ions diffuse into the second fin portions to form a second punch-through preventing layer; and

performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.

11. The method of claim 10, wherein the second punch-through preventing ions are implanted into the PMOS region of the substrate by using a lateral straggle ion implantation process.

12. The method of claim 10, wherein:

the first punch-through preventing ions are P-type ions including fluoride ions, or boron difluoride; and

the second punch-through preventing ions are N-type ions including arsenic ions.

13. The method of claim 10, wherein:

after performing the annealing process, a doping concentration of the first punch-through preventing ions in the first punch-through preventing layer is in a range from 1.0E18 atom/cm³ to 5.0E19 atom/cm³, and a doping concentration of the second punch-through preventing ions in the second punch-through preventing layer is in a range from 1.0E18 atom/cm³ to 5.0E19 atom/cm³.

14. The method of claim 10, further comprising:

after performing the annealing process, forming a first threshold voltage adjusting layer in the first fin portions, and a second threshold voltage adjusting layer in the second fin portions;

wherein the first threshold voltage adjusting layer is located just above the first punch-through preventing layer, the second threshold voltage adjusting layer is located just above the second punch-through preventing layer.

15. The method of claim 10, further comprising:

after forming the insulating structure and before performing the annealing process, implanting diffusion preventing ions into insulating structure in the NMOS region, and making the diffusion preventing ions enter the first punch-through preventing layer to prevent a diffusion of the first punch-through preventing ions;

wherein after performing the annealing process, a doping concentration of the diffusion ions in the first punch-through preventing layer is in a range from 1.0E19 atom/cm³ to 5.0E20 atom/cm³.

16. The method of claim 15, wherein the diffusion preventing ions include carbon ions and nitrogen ions, and are implanted into insulating structure in the NMOS region by using a composite ions implantation process.

17. The method of claim 15, wherein the diffusion preventing ions are implanted into insulating structure in the NMOS region by using a lateral straggle ion implantation process.

18. The method of claim 10, wherein forming the insulating structure comprises:

forming an insulating material layer, a top surface of the insulating layer is non-lower than the top surfaces of the fin portions; and

etching the insulating material layer to make the top surface of the insulating layer lower than the top surfaces of the fin portions to form the insulating structure.

19. The method of claim 18, wherein:

the insulating material layer is formed by using a flowable chemical vapor deposition process, including;

forming a precursor layer, a surface of the precursor layer is non-lower than the top surfaces of the fin portions; and

curing the precursor layer to form the insulating material layer by using a low-temperature annealing process, wherein a temperature of the low-temperature annealing process is in a range from 500°

C. to 600°

C., a duration time of the low-temperature annealing process is in a range from 20 minutes to 40 minutes.