Multi terminal capacitor within input output path of semiconductor package interconnect
First Claim
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1. A semiconductor chip system comprising:
- a semiconductor chip electrically connected to a chip carrier via first input output (IO) interconnects within a first interconnect level between a bottom surface of the semiconductor chip and an upper surface of the chip carrier;
a carrier interposer electrically connected to the chip carrier via second IO interconnects within a second interconnect level between a bottom surface of the chip carrier and an upper surface of the carrier interposer and electrically connected to a mother board via third IO interconnects within a third interconnect level between a bottom surface of the carrier interposer and an upper surface of the mother board;
a multi terminal capacitor within the second interconnect level such that there is no inductance between a first solder interconnect within the second interconnect level and a first terminal of the multi terminal capacitor and between the first solder interconnect and a first IO contact of the chip carrier and such that there is no inductance between a second solder interconnect within the second interconnect level and a second terminal of the multi terminal capacitor and between the second solder interconnect and a second IO contact of the chip carrier, wherein the second IO contact of the chip carrier diagonally neighbors the first IO contact of the chip carrier.
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Abstract
A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
20 Citations
10 Claims
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1. A semiconductor chip system comprising:
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a semiconductor chip electrically connected to a chip carrier via first input output (IO) interconnects within a first interconnect level between a bottom surface of the semiconductor chip and an upper surface of the chip carrier; a carrier interposer electrically connected to the chip carrier via second IO interconnects within a second interconnect level between a bottom surface of the chip carrier and an upper surface of the carrier interposer and electrically connected to a mother board via third IO interconnects within a third interconnect level between a bottom surface of the carrier interposer and an upper surface of the mother board; a multi terminal capacitor within the second interconnect level such that there is no inductance between a first solder interconnect within the second interconnect level and a first terminal of the multi terminal capacitor and between the first solder interconnect and a first IO contact of the chip carrier and such that there is no inductance between a second solder interconnect within the second interconnect level and a second terminal of the multi terminal capacitor and between the second solder interconnect and a second IO contact of the chip carrier, wherein the second IO contact of the chip carrier diagonally neighbors the first IO contact of the chip carrier. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor chip system comprising:
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a semiconductor chip electrically connected to a chip carrier via first input output (IO) interconnects within a first interconnect level between a bottom surface of the semiconductor chip and an upper surface of the chip carrier; a carrier interposer electrically connected to the chip carrier via second IO interconnects within a second interconnect level between a bottom surface of the chip carrier and an upper surface of the carrier interposer and electrically connected to a mother board via third IO interconnects within a third interconnect level between a bottom surface of the carrier interposer and an upper surface of the mother board; a multi terminal capacitor within the second interconnect level such that there is no inductance between a first solder interconnect within the second interconnect level and a first terminal of the multi terminal capacitor and between the first solder interconnect and a first IO contact of the carrier interposer and such that there is no inductance between a second solder interconnect within the second interconnect level and a second terminal of the multi terminal capacitor and between the second solder interconnect and a second IO contact of the carrier interposer, wherein the second IO contact of the carrier interposer diagonally neighbors the first IO contact of the carrier interposer. - View Dependent Claims (7, 8, 9, 10)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsArvin, Charles L., Audet, Jean, Quinlan, Brian W., Reynolds, Charles L., Sundlof, Brian R.
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Primary Examiner(s)Moore, Whitney
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Application NumberUS15/796,770Publication NumberTime in Patent Office493 DaysField of SearchNoneUS Class CurrentCPC Class CodesH01L 2224/13101 the principal constituent m...H01L 2224/16225 the item being non-metallic...H01L 2224/16265 the item being a discrete p...H01L 2224/2919 with a principal constituen...H01L 2224/32225 the item being non-metallic...H01L 2224/73204 the bump connector being em...H01L 2224/73253 Bump and layer connectorsH01L 2224/81815 Reflow solderingH01L 23/3675 characterised by the shape ...H01L 23/49816 Spherical bumps on the subs...H01L 23/49822 Multilayer substrates multi...H01L 23/49894 Materials of the insulating...H01L 23/50 for integrated circuit devi...H01L 23/5223 Capacitor integral with wir...H01L 24/13 of an individual bump conne...H01L 24/16 of an individual bump conne...H01L 24/17 of a plurality of bump conn...H01L 24/29 of an individual layer conn...H01L 24/32 of an individual layer conn...H01L 24/48 of an individual wire conne...View All
