Multi terminal capacitor within input output path of semiconductor package interconnect

• US 10,224,274 B2
• Filed: 10/28/2017
• Issued: 03/05/2019
• Est. Priority Date: 07/11/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arvin, Charles L., Audet, Jean, Quinlan, Brian W., Reynolds, Charles L., Sundlof, Brian R.
• Primary Examiner(s): Moore, Whitney
• Application Number:
  US15/796,782
• Publication Number:
  US 20180068945A1
• Time in Patent Office: 493 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 2201/10015 : Non-printed capacitor

Abstract

A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

Claims

1. A semiconductor device fabrication method comprising:

attaching a multi terminal capacitor to neighboring IO contacts of a semiconductor chip carrier such that a first terminal contacts a first IO contact and a second terminal contacts a second IO contact; and

interconnecting the semiconductor chip carrier with a carrier interposer with solder interconnects such that a first solder interconnect directly contacts the first terminal and the first IO contact and a second solder interconnect directly contacts the second terminal and the second IO contact.

2. The semiconductor device fabrication method of claim 1, wherein there is no inductance between the first solder interconnect and the first terminal and between the first solder interconnect and the first IO contact.

3. The semiconductor device fabrication method of claim 1, further comprising:

placing the first solder interconnect upon the first IO contact; and

placing the second solder interconnect upon the second IO contact.

4. The semiconductor device fabrication method of claim 1, further comprising:

reflowing the solder interconnects.

5. The semiconductor device fabrication method of claim 1, wherein the multi terminal capacitor is attached to an underside of the chip carrier.

6. The semiconductor device fabrication method of claim 1, wherein the first IO contact and the second IO contact are horizontally neighboring IO contacts.

7. The semiconductor device fabrication method of claim 1, wherein the first IO contact and the second IO contact are vertically neighboring IO contacts.

8. The semiconductor device fabrication method of claim 1, wherein the first IO contact and the second IO contact are diagonal neighboring IO contacts.

9. The semiconductor device fabrication method of claim 1, wherein the first IO contact and the second IO contact are vertically neighboring IO contacts.

10. The semiconductor device fabrication method of claim 1, wherein the first IO contact and the second IO contact are diagonal neighboring IO contacts.

11. A semiconductor device fabrication method comprising:

attaching a multi terminal capacitor to neighboring IO contacts of a carrier interposer such that a first terminal contacts a first IO contact and a second terminal contacts a second IO contact; and

interconnecting the carrier interposer with a semiconductor chip carrier with solder interconnects such that a first solder interconnect directly contacts the first terminal and the first IO contact and a second solder interconnect directly contacts the second terminal and the second IO contact.

12. The semiconductor device fabrication method of claim 11, wherein there is no inductance between the first solder interconnect and the first terminal and between the first solder interconnect and the first IO contact.

13. The semiconductor device fabrication method of claim 11, further comprising:

placing the first solder interconnect upon the first IO contact; and

placing the second solder interconnect and upon the second IO contact.

14. The semiconductor device fabrication method of claim 11, further comprising:

reflowing the solder interconnects.

15. The semiconductor device fabrication method of claim 11, wherein the multi terminal capacitor is attached to a topside of the carrier interposer.

16. The semiconductor device fabrication method of claim 11, wherein the first IO contact and the second IO contact are horizontally neighboring IO contacts.