Semiconductor device and structure

• US 10,224,279 B2
• Filed: 07/31/2015
• Issued: 03/05/2019
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Nguyen, Sophia
• Application Number:
  US14/814,865
• Publication Number:
  US 20150340316A1
• Time in Patent Office: 1,313 Days
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A 3D device, including: a first layer including a first memory including a first transistor; a second layer including a second memory including a second transistor; and a Resistive RAM structure, where the second transistor is self-aligned to the first transistor, and where the Resistive RAM structure is overlaying the first layer and is overlaid by the second layer.

Claims

1. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor;

a second layer comprising a second memory comprising a second transistor;

a Resistive RAM structure,

wherein said second transistor is self-aligned to said first transistor, and

wherein said Resistive RAM structure is overlaying said first layer and is overlaid by said second layer; and

at least one horizontally oriented silicon strip,

wherein said Resistive RAM structure is designed to be connected to said silicon strip.

2. The 3D device according to claim 1,

wherein said first transistor comprises a single crystal channel.

3. The 3D device according to claim 1, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

4. The 3D device according to claim 1,

wherein said second layer comprises a third transistor connected to said second transistor.

5. The 3D device according to claim 1, further comprising:

at least one logic transistor disposed underneath or above said first memory;

a vertical control line connecting said at least one logic transistor to said first transistor.

6. The 3D device according to claim 1,

wherein said device comprises a word-line controlling said first transistor and said second transistor.

7. The 3D device according to claim 1,

wherein said Resistive RAM structure is in-parallel to said first horizontally oriented silicon strip.

8. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor;

a second layer comprising a second memory comprising a second transistor;

a Resistive RAM structure;

a first horizontally oriented silicon strip; and

a second horizontally oriented silicon strip,

wherein said second transistor is self-aligned to said first transistor, and

wherein said Resistive RAM structure is in-parallel to said first horizontally oriented silicon strip and said second horizontally oriented silicon strip.

9. The 3D device according to claim 8,

wherein said first transistor comprises a single crystal channel.

10. The 3D device according to claim 8,

wherein said Resistive RAM structure is designed to be connected to said first horizontally oriented silicon strip and said second horizontally oriented silicon strip.

11. The 3D device according to claim 8, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

12. The 3D device according to claim 8,

wherein said second layer comprises a third transistor connected to said second transistor.

13. The 3D device according to claim 8, further comprising:

at least one logic transistor disposed underneath or above said first memory;

a vertical control line connecting said at least one logic transistor to said first transistor.

14. The 3D device according to claim 8,

wherein said device comprises a word-line controlling said first transistor and said second transistor.

15. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor;

a second layer comprising a second memory comprising a second transistor;

a first Resistive RAM structure; and

a second Resistive RAM structure,

wherein said second transistor is self-aligned to said first transistor, and

wherein said first Resistive RAM structure is self-aligned to said second Resistive RAM structure, and

wherein said first Resistive RAM structure and said second Resistive RAM structure are not in contact.

16. The 3D device according to claim 15,

wherein said first transistor comprises a single crystal channel.

17. The 3D device according to claim 15, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

18. The 3D device according to claim 15,

wherein said second layer comprises a third transistor connected to said second transistor.

19. The 3D device according to claim 15, further comprising:

at least one logic transistor disposed underneath or above said first memory,

a vertical control line connecting at least one logic transistor to said first transistor.

20. The 3D device according to claim 15,

wherein said device comprises a word-line controlling said first transistor and said second transistor.