Semiconductor device

• US 10,224,294 B2
• Filed: 03/02/2016
• Issued: 03/05/2019
• Est. Priority Date: 08/18/2015
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Nishizawa, Koichiro, Hisaka, Takayuki
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US15/735,858
• Publication Number:
  US 20180138132A1
• Time in Patent Office: 1,098 Days
• CPC Class Codes: H01L 21/4817 for containers, e.g. caps H01L21/4871 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13294 with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
• CPC Class Codes: H01L 2224/13339 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13344 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13347 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13364 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13369 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/451 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/83447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83484 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06537 : Electromagnetic shielding
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/02 : Containers; Seals H01L23/12, H01L23/34, H01L23/48, H01L23/552, H01L23/66 take precedence; for memories G11C
• CPC Class Codes: H01L 23/04 : characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/041 : the container being a hollow construction having no base used as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/12 : Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/14 : characterised by the material or its electrical properties printed circuit boards H05K1/00
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 29/812 : with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/13051 : Heterojunction bipolar transistor [HBT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

Claims

1. A semiconductor device comprising:

a device substrate having a front surface and a back surface;

a semiconductor circuit provided on the front surface of the device substrate;

a sealing frame bonded to the front surface of the device substrate and surrounding the semiconductor circuit;

a cap substrate having a front surface and a back surface, wherein the front surface of the cap substrate is bonded to the whole perimeter of the sealing frame while covering the semiconductor circuit to form a hollow part provided between the device substrate and the cap substrate and housing the semiconductor circuit in an airtight state;

a plurality of via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, the plurality of via portions penetrating the device substrate, and the plurality of via portions connected to the semiconductor circuit; and

a plurality of bump portions respectively provided at positions of the via portions in the hollow part and connecting the via portions to the cap substrate, wherein

at least one of the plurality of bump portions is not grounded via any of the plurality of via portions, and

at least another of the plurality of bump portions is grounded via at least one of the plurality of via portions.

2. The semiconductor device according to claim 1, wherein at least a part of the bump portions is formed of a conductive material, and

a conductive film is provided on the front surface of the cap substrate and covers the front surface of the cap substrate while being insulated from some of the part of the bump portions not grounded via the via portions.

3. The semiconductor device according to claim 1, wherein at least a part of the bump portions is formed of a conductive material,

the part of the bump portions not grounded via the via portions includes an insulating material, and

a conductive film is provided on the front surface of the cap substrate and covers the entire front surface of the cap substrate.

4. The semiconductor device according to claim 1, wherein the plurality of via portions are a plurality of first via portions, and the plurality of bump portions are first bump portions, the semiconductor device comprising:

a plurality of second via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, the plurality of second via portions penetrating the cap substrate, and the plurality of second via portions connected to the semiconductor circuit; and

second bump portions located in the hollow part with the first bump portions, the second bump portions provided at positions of the second via portions of the cap substrate, and the second bump portions connecting the second via portions to the device substrate.

5. The semiconductor device according to claim 4, wherein at least the second bump portions are formed of a conductive material, and

a conductive film is provided on the front surface of the cap substrate and covers the front surface while being insulated from the second bump portions.

6. The semiconductor device according to claim 4, comprising a single conductive film formed on the back surface of the device substrate and connected to the semiconductor circuit via the first via portions formed in the device substrate.

8. The semiconductor device according to claim 1, wherein a conductive layer is conformally formed in at least one of the via portions of the device substrate or in a through hole of the cap substrate, and the conductive layer includes a cavity.

9. The semiconductor device according to claim 1, wherein the sealing frame is formed of a conductive material.

10. The semiconductor device according to claim 1, wherein the bump portions and the sealing frame are formed of Au, Ag, Cu, Pt, Pd or an alloy of those metals.

11. The semiconductor device according to claim 1, wherein the sealing frame and the bump portions are formed of the same material.

12. The semiconductor device according to claim 1, wherein the device substrate and the cap substrate are formed of the same material.

13. The semiconductor device according to claim 1, wherein the sealing frame and the bump portions are formed to the same height, and the device substrate and the cap substrate are formed into a tabular shape where no concave part exists.

14. The semiconductor device according to claim 1, comprising another semiconductor circuit provided on the back surface side of a common substrate provided between the device substrate and the cap substrate.

18. The semiconductor device according to claim 1, wherein at least one of the bump portions is formed such that a shape of the at least one of the bump portions projected onto a plane perpendicular to the front surfaces of the device and cap substrates is rectangular.

7. A semiconductor device comprising:

a device substrate having a front surface and a back surface;

a semiconductor circuit provided on the front surface of the device substrate;

a sealing frame bonded to the front surface of the device substrate and surrounding the semiconductor circuit;

a cap substrate having a front surface and a back surface, wherein the front surface of the cap substrate is bonded to the sealing frame while covering the semiconductor circuit to form a hollow part provided between the device substrate and the cap substrate and housing the semiconductor circuit in an airtight state;

a plurality of first via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, the plurality of first via portions penetrating the device substrate, and the plurality of first via portions connected to the semiconductor circuit;

a plurality of first bump portions respectively provided at positions of the first via portions in the hollow part and connecting the first via portions to the cap substrate;

a plurality of second via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, the plurality of second via portions penetrating the cap substrate, and the plurality of second via portions connected to the semiconductor circuit;

second bump portions located in the hollow part with the first bump portions, the second bump portions provided at positions of the second via portions of the cap substrate, and the second bump portions connecting the second via portions to the device substrate; and

an input electrode, an output electrode, and a ground electrode which are connected to the semiconductor circuit,

wherein at least the second bump portions of the bump portions are formed of a conductive material,

the input electrode and the output electrode are formed on the back surface of the cap substrate and connected to the semiconductor circuit via the second via portions of the cap substrate and the second bump portions, and

the ground electrode is formed of a conductive film covering the entire back surface of the device substrate and connected to the semiconductor circuit via the first via portions of the device substrate.

15. A semiconductor device comprising:

two substrates including opposite surfaces facing to each other and forming a hollow part between the opposite surfaces;

electrode pads formed on the opposite surfaces of the substrates;

a semiconductor circuit housed in the hollow part in an airtight state and connected to at least one of the electrode pads;

a via portion formed in at least one of the substrates, and including a via hole penetrating at least one of the substrates and opened on a back surface side of one of the electrode pads, and a filler metal filling the via hole and connected to the one of the electrode pads; and

a bump portion formed as a cylindrical hollow structure including a cavity therein, and bonded to the electrode pad of one of the substrates and the electrode pad of the other of the substrates, wherein

the via portion comprises a plurality of via portions,

the bump portion comprises a plurality of bump portions,

at least one of the plurality of bump portions is not grounded via any of the plurality of via portions, and

at least another of the plurality of bump portions is grounded via at least one of the plurality of via portions.

16. The semiconductor device according to claim 15, the bump portion is located outside an opening end of the via hole over an entire circumference of the via hole opened on a back surface side of the electrode pad connected to the bump portion.

17. The semiconductor device according to claim 15, wherein the bump portion includes:

a first bump layer formed as a columnar solid structure with no cavity inside, connected to the electrode pad of one of the substrates, and separated from the electrode pad of the other of the substrates; and

a second bump layer formed as a cylindrical hollow structure including a cavity therein, laminated with the first bump layer in a direction perpendicular to the opposite surfaces of the substrates, and bonded to the first bump layer and the electrode pad of the other of the substrates.

19. The semiconductor device according to claim 15, wherein the bump portion is formed of Au, Ag, Cu, Pt, Pd or an alloy of those metals.