Semiconductor device and method of manufacturing the same

• US 10,224,428 B2
• Filed: 10/03/2017
• Issued: 03/05/2019
• Est. Priority Date: 11/14/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tokuda, Satoru
• Primary Examiner(s): Patel, Reema
• Application Number:
  US15/723,662
• Publication Number:
  US 20180138311A1
• Time in Patent Office: 518 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area.

The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface that is an opposite surface of the first surface;

a drain region which is arranged in the semiconductor substrate and has a first conductivity type;

a drift region which is arranged on a side of the drain region facing the first surface in the semiconductor substrate and has the first conductivity type;

a base region which is arranged on a side of the drift region facing the first surface in the semiconductor substrate and has a second conductivity type opposite to the first conductivity type;

a source region which is arranged on a side of the base region facing the first surface so that the base region is sandwiched between the source region and the drift region in the semiconductor substrate and which has the first conductivity type;

a gate electrode which faces a part of the base region sandwiched between the source region and the drift region while being insulated from the part of the base region;

an interlayer insulating film which is arranged over the first surface;

a conductive layer which is arranged in the interlayer insulating film and is electrically coupled to the drain region;

a wiring line which is arranged over the interlayer insulating film; and

a contact plug which is arranged in the interlayer insulating film and is electrically coupled to the wiring line and the source region,

wherein the interlayer insulating film has an intermediate interlayer insulating film arranged between the conductive layer and the contact plug,

wherein the conductive layer is formed of a conductor which changes into an insulator when being oxidized, and

wherein the intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.

2. The semiconductor device according to claim 1, further comprising:

a column region which extends from the base region toward the second surface and has the second conductivity type.

3. The semiconductor device according to claim 1,

wherein the interlayer insulating film further includes an upper interlayer insulating film which is arranged on a side of the conductive layer facing the wiring line, and

wherein the semiconductor device further includes an oxidation-resistant film which is arranged over the upper interlayer insulating film and is formed of a material that is more difficult to be oxidized than the upper interlayer insulating film.

4. The semiconductor device according to claim 1,

wherein the interlayer insulating film further includes a lower interlayer insulating film which is arranged on a side of the conductive layer facing the first surface and an upper interlayer insulating film which is arranged on a side of the conductive layer facing the wiring line, and

wherein the upper interlayer insulating film and the lower interlayer insulating film are CVD films.

5. The semiconductor device according to claim 4,

wherein the conductive layer is formed of a polycrystalline silicon in which impurities are doped.

6. The semiconductor device according to claim 5,

wherein the impurities are elements to be donors of the polycrystalline silicon.

7. A method of manufacturing a semiconductor device, the method comprising the step of:

preparing a semiconductor substrate having a first surface and a second surface that is a surface opposite to the first surface,

wherein in the semiconductor substrate,

a drain region which has a first conductivity type,

a drift region which is arranged on a side of the drain region facing the first surface and has the first conductivity type,

a base region which is arranged on a side of the drift region facing the first surface and has a second conductivity type opposite to the first conductivity type, and

a source region which is arranged on a side of the base region facing the first surface so that the base region is sandwiched between the source region and the drift region and which has the first conductivity type, are formed, and

wherein the method further includes the steps of

forming a gate electrode which faces a part of the base region sandwiched between the source region and the drift region while being insulated from the part of the base region,

forming a lower interlayer insulating film over the first surface,

forming a conductive layer over the lower interlayer insulating film,

forming an upper interlayer insulating film over the conductive layer,

forming a mask having an opening over the upper interlayer insulating film,

forming an upper contact hole that penetrates the upper interlayer insulating film and the conductive layer by etching the upper interlayer insulating film and the conductive layer through the opening and exposing the conductive layer from a side wall of the contact hole, and

forming an intermediate interlayer insulating film by thermally oxidizing the conductive layer exposed from the side wall.

8. The method of manufacturing a semiconductor device according to claim 7,

wherein the thermal oxidation is wet oxidation.

9. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of:

after forming the intermediate interlayer insulating film, removing the mask.

10. The method of manufacturing a semiconductor device according to claim 7,

wherein the mask is an oxidation-resistant film formed of a material that is more difficult to be oxidized than the upper interlayer insulating film.

11. The method of manufacturing a semiconductor device according to claim 10,

wherein the upper interlayer insulating film is a silicon oxide film, and

wherein the oxidation-resistant film is a silicon nitride film or a silicon oxynitride film.

12. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of:

after forming the mask, forming a wiring line over the mask.