Dual signal protocol input/output (I/O) buffer circuit

• US 10,224,911 B1
• Filed: 03/31/2016
• Issued: 03/05/2019
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Tan, Tat Hin, Wong, Choong Kit, Lau, Ker Yon, Su, Hsiao Wei, Ng, Hoong Chin
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/086,887
• Time in Patent Office: 1,069 Days
• Field of Search: None
• CPC Class Codes: H03K 5/007 Base line stabilisation thresholding H03K5/08

Abstract

An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.

Claims

1. An integrated circuit device, comprising:

a first input/output (I/O) buffer circuit transferring signals based on a given signal transmission protocol selected from a group of signal transmission protocols, wherein the first input/output buffer circuit comprises;

first and second groups of stacked transistors, wherein the first group of stacked transistors transfers signals formatted in accordance with a first signal transmission protocol from the group of signal transmission protocols, and the second group of stacked transistors transfers the signals formatted in accordance to a plurality of signal transmission protocols from the group of signal transmission protocols, wherein the first input/output buffer circuit transfers the signals formatted in accordance with the first signal transmission protocol by activating both the first and second groups of stacked transistors, and wherein the first input/output buffer circuit transfers the signals formatted in accordance with the second signal transmission protocol by activating only one of the first and second groups of stacked transistors and biasing a subset of the transistors in the selectively activated one of the first and second groups of stacked transistors at an intermediate voltage that is different from voltages applied to activate or deactivate transistors, wherein the group of signal transmission protocols includes a single ended signal transmission protocol and a differential signal transmission protocol.

2. The integrated circuit device as defined in claim 1, the integrated circuit device further comprising:

a second input/output buffer circuit configurable to transfer signals based on the given signal transmission protocol selected from the group of signal transmission protocols, wherein the second input/output buffer circuit comprises;

third and fourth groups of stacked transistors, wherein the third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols, and the fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.

3. The integrated circuit device as defined in claim 2, wherein each of the first, second, third and fourth groups of stacked transistors comprises:

two p-channel transistors that are coupled in series between a middle node and a power terminal; and

two n-channel transistors that are coupled in series between the middle node and a ground terminal, and wherein the two n-channel transistors are coupled in series with the two p-channel transistors.

4. The integrated circuit device as defined in claim 3, further comprising:

a first input/output pad, wherein, the middle nodes of the first and second groups of stacked transistors are both coupled to the first input/output pad;

a second input/output pad, wherein the middle nodes of the third and fourth stacked transistors are both coupled to the second input/output pad.

5. The integrated circuit device as defined in claim 4, wherein the first and second groups of stacked transistors are coupled in parallel, and wherein the third and fourth groups of stacked transistors are coupled in parallel.

6. The integrated circuit device as defined in claim 5, wherein the first and second input/output buffers are selected from a group of circuits consisting of:

current mode LVDS protocol circuits and voltage mode LVDS protocol circuits.

7. An integrated circuit device, comprising:

a first input/output (I/O) buffer circuit that transfers signals in accordance to a given signal transmission protocol selected from first and second signal transmission protocols; and

a second input/output (I/O) buffer circuit that transfer signals in accordance to the given signal transmission protocol, wherein a first subset of transistors in the second I/O buffer circuit is deactivated by biasing the first subset of transistors with a first voltage when the second I/O buffer circuit transfers signals in accordance to the given signal transmission protocol, wherein a second subset of transistors in the second I/O buffer circuit is activated by biasing the second subset of transistors with a second voltage when the second I/O buffer circuit transfers signals in accordance to the given signal transmission protocol, and wherein a third subset of transistors in the second I/O buffer circuit is biased at an intermediate voltage that is between the first and second voltages; and

interconnections coupled to the first and second I/O buffer circuits, wherein the signal interconnections are disabled when the first and second I/O buffer circuits are configured to receive signals according to either the first or second signal transmission protocols.

8. The integrated circuit device as defined in claim 7, further comprising:

a node stabilization circuit that is coupled to one of the interconnections, wherein the node stabilization circuit stabilizes a voltage level of the one of the interconnections.

9. The integrated circuit device as defined in claim 8, further comprising:

a current source that is coupled to one of the interconnections, wherein the current source comprises a p-channel transistor.

10. The integrated circuit device as defined in claim 7, further comprising:

a first pass gate transistor that comprises a p-channel transistor that is coupled in series to a first interconnection of the interconnections; and

a second pass gate transistor that comprises an n-channel transistor that is coupled in series to a second interconnection of the interconnections.

11. The integrated circuit device as defined in claim 7, wherein the first signal transmission protocol is a double data rate (DDR) signal transmission protocol and the second signal transmission protocol is a low voltage differential signal (LVDS) protocol.

12. The integrated circuit device as defined in claim 7, wherein the first input/output buffer circuit comprises:

two groups of stacked transistors that are formed in parallel to each other, wherein each of the two groups of stacked transistors comprises a pull-up circuit coupled in series to a pull-down circuit;

an input/output pad that is coupled to a node between the pull-up circuit and the pull-down circuit of each of the two groups of stacked transistors.

13. The integrated circuit device as defined in claim 12, wherein the second input/output buffer circuit comprises:

two groups of stacked transistors that are formed parallel to each other, wherein each of the two groups of stacked transistors comprises a pull-up circuit coupled in series to a pull-down circuit;

another input/output pad that is coupled to a node between the pull-up circuit and the pull-down circuit of each of the two groups of stacked transistors.

14. A method of operating an integrated circuit device that comprises first, second, third and fourth groups of stacked transistors, wherein the method comprises:

receiving configuration information for the first, second, third and fourth groups of stacked transistors; and

configuring the first, second, third and fourth stacked transistors using the received configuration information to transfer signals in accordance to a selected signal transmission protocol from a group of first and second signal transmission protocols, wherein transmitting signals according to the first signal transmission protocol comprises activating the first, second, third, and fourth groups of stacked transistors, and wherein transmitting signals according to the second signal transmission protocol comprises activating only the first and third groups of stacked transistors by biasing a first transistor in the first group of stacked transistors at a first voltage, biasing a second transistor in the first group of stacked transistors at an second voltage that is less than the first voltage, and biasing a third transistor in the second group of stacked transistors at a third voltage, wherein the first signal transmission protocol is a double data rate signal transmission protocol and the second signal transmission protocol is a low voltage differential single (LVDS) protocol.

15. The method as defined in claim 14, wherein the first, second, third and fourth groups of stacked transistors are configured to transmit signals in accordance to the first signal transmission protocol, the method further comprising:

activating the first, second, third and fourth group of stacked transistors;

transmitting a signal formatted in accordance with the first signal transmission protocol from a pad that is coupled to the first and second groups of stacked transistors; and

transmitting another signal formatted in accordance with the first signal transmission protocol from another pad that is coupled to the third and fourth groups of stacked transistors.

16. The method as defined in claim 14, wherein the first, second, third and fourth groups of stacked transistors are configured to receive signals according to the first signal transmission protocol, the method further comprising:

activating the first and third groups of stacked transistors;

disabling the second and fourth groups of stacked transistors; and

receiving a signal formatted in accordance with the first signal transmission protocol from a pad that is coupled to the first and second groups of stacked transistors.

17. The method as defined in claim 14, wherein the first, second, third and fourth groups of stacked transistors are configured to transmit signals formatted in accordance with the second signal transmission protocol, the method further comprising:

disabling the second and fourth groups of stacked transistors;

biasing the first and third groups of stacked transistors;

transmitting a first signal formatted in accordance to the second signal transmission protocol out from a pad that is coupled to the first and second groups of stacked transistors; and

transmitting a second signal formatted in accordance with the second signal transmission protocol and that is complement to the first signal from another pad that is coupled to the third and fourth groups of stacked transistors.

18. The method as defined in claim 14, wherein the first, second, third and fourth groups of stacked transistors are configured to receive signals out according to the second signal transmission protocol, the method comprising:

disabling the second and fourth groups of stacked transistors; and

activating transistors within the first group of stacked transistors that are coupled to a pad of the first and second group of stacked transistors; and

activating transistors within the third group of stacked transistors that are coupled to a pad of the third and fourth group of stacked transistors.

19. The method as defined in claim 14, wherein the first, second, third and fourth groups of stacked transistors are configured in accordance to the first signal transmission protocol, the method further comprising:

receiving another configuration information that comprises configuration information for the first, second, third and fourth groups of stacked transistors to transfer signals formatted in accordance with the second signal transmission protocol; and

configuring first, second, third and fourth groups of stacked transistors using the received configuration information to transfer signals formatted in accordance with to the second signal transmission protocol.