Shared cycle LSB generation for an array of successive approximation analog-to-digital converters

• US 10,224,949 B1
• Filed: 07/26/2018
• Issued: 03/05/2019
• Est. Priority Date: 07/26/2018
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Li, Zheming, Lo, Steve Chikin, Liu, Chunbo
• Primary Examiner(s): Jeanglaude, Jean B
• Application Number:
  US16/046,187
• Time in Patent Office: 222 Days
• Field of Search: 341161, 341145, 341155, 341156, 341118
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register
• CPC Class Codes: H03M 1/466 using switched capacitors

Abstract

An example apparatus for converting a plurality of analog signals to a plurality of digital signals includes: a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive a respective one of the plurality of analog signals, a second input configured to receive a reference signal, and an output configured to provide a respective one of the plurality of digital signals; and a shared cycle LSB generator coupled to the plurality of SAR ADCs and configured to provide the reference signal shared by the plurality of SAR ADCs.

Claims

1. An apparatus for converting a plurality of analog signals to a plurality of digital signals, comprising:

a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive a respective one of the plurality of analog signals, a second input configured to receive a cycle LSB signal, and an output configured to provide a respective one of the plurality of digital signals; and

a shared cycle LSB generator coupled to the plurality of SAR ADCs and configured to provide the cycle LSB signal shared by the plurality of SAR ADCs.

2. The apparatus of claim 1, wherein each of the plurality of SAR ADCs comprises:

a first capacitor configured to supply an input signal;

a reference input circuit configured to adjust the input signal in response to the cycle LSB signal and a control signal;

a comparator having a first input coupled to the first capacitor, a second input configured to receive a constant reference voltage, and an output; and

SAR logic coupled to the output of the comparator and configured to generate the control signal and a respective one of the plurality of digital signals.

3. The apparatus of claim 1, wherein the shared cycle LSB generator comprises:

a digital-to-analog converter (DAC) having an output; and

a voltage amplifier coupled to the output of the DAC and configured to provide the cycle LSB signal.

4. The apparatus of claim 2, wherein the reference input circuit of each of the plurality of SAR ADCs comprises:

a switched capacitor circuit coupled between an output of the shared cycle LSB generator and the first input of the comparator.

5. The apparatus of claim 4, wherein the switched capacitor circuit comprises:

a first capacitor having a top plate and a bottom plate, the top plate thereof coupled to the output of the shared cycle LSB generator, the top and bottom plates thereof switchably coupled to a constant bias voltage and switchably coupled to the first input of the comparator; and

a second capacitor having a top plate and a bottom plate, the top plate thereof coupled to the output of the shared cycle LSB generator, the top and bottom plates thereof switchably coupled to the constant bias voltage and switchably coupled to the first input of the comparator.

6. The apparatus of claim 4, wherein the switched capacitor circuit comprises:

only one capacitor having a top plate and a bottom plate, the top plate thereof coupled to the output of the shared cycle LSB generator, the top and bottom plates thereof switchably coupled to a constant bias voltage and switchably coupled to the first input of the comparator.

7. The apparatus of claim 4, wherein the switched capacitor circuit comprises:

first, second, and third capacitors each having a top plate switchably coupled to the first input of the comparator and each having a bottom plate coupled to ground;

wherein the output of the shared cycle LSB generator includes a first output switchably coupled to the top plate of each of the first, second, and third capacitors and a second output switchably coupled to the top plate of each of the first, second, and third capacitors.

8. The apparatus of claim 4, wherein the switched capacitor circuit comprises:

only one capacitor having a top plate switchably coupled to the first input of the comparator and having a bottom plate coupled to ground;

wherein the output of the shared cycle LSB generator includes a first output switchably coupled to the top plate of the capacitor and a second output switchaby coupled to the top plate of the capacitor.

9. The apparatus of claim 4, wherein the reference input circuit of each of the plurality of SAR ADCs comprises:

first, second, third, and fourth capacitors each having a top plate switchably coupled to the first and second inputs of the comparator and each having a bottom plate coupled to ground;

wherein the output of the shared cycle LSB generator includes a first output switchably coupled to the top plate of each of the first, second, third and fourth capacitors and a second output switchably coupled to the top plate of each of the first, second, third, and fourth capacitors.

10. The apparatus of claim 4, wherein the reference input circuit of each of the plurality of SAR ADCs comprises:

first and second capacitors each having a top plate switchably coupled to the first and second inputs of the comparator and each having a bottom plate coupled to ground;

wherein the output of the shared cycle LSB generator includes a first output switchably coupled to the top plate of each of the first and second capacitors and a second output switchably coupled to the top plate of each of the first and second capacitors.

11. An integrated circuit (IC), comprising:

a plurality of analog front ends (AFEs) configured to provide a plurality of analog signals;

a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive one of the plurality of analog signals, a second input configured to receive a cycle LSB signal, and an output configured to provide a digital signal;

a shared cycle LSB generator coupled to the plurality of SAR ADCs and configured to provide the cycle LSB signal shared by the plurality of SAR ADCs; and

a processing system configured to process the digital signal output from each of the plurality of SAR ADCs.

12. The IC of claim 11, wherein each of the plurality of SAR ADCs comprises:

a first capacitor configured to supply an input signal;

a reference input circuit configured to adjust the input signal in response to the cycle LSB signal and a control signal;

a comparator having a first input coupled to the first capacitor, a second input configured to receive a constant reference voltage, and an output; and

SAR logic coupled to the output of the comparator and configured to generate the control signal and the digital signal output from the respective SAR ADC.

13. The IC of claim 11, wherein the shared cycle LSB generator comprises:

a digital-to-analog converter (DAC) having an output; and

a voltage amplifier coupled to the output of the DAC and configured to provide the cycle LSB signal as voltages shared by the plurality of SAR ADCs.

14. The IC of claim 12, wherein the reference input circuit of each of the plurality of SAR ADCs comprises:

a switched capacitor circuit coupled between an output of the shared cycle LSB generator and the first input of the comparator.

15. The IC of claim 11, wherein the shared cycle LSB generator comprises:

a digital-to-analog converter (DAC) having an output; and

a current amplifier coupled to the output of the DAC and configured to provide the cycle LSB signal as currents shared by the plurality of SAR ADCs.

16. The IC of claim 11, wherein the shared cycle LSB generator comprises:

a digital-to-analog converter (DAC) having an output;

an electrical charge generating circuit coupled to the output of the DAC and configured to provide the cycle LSB signal as electrical charges shared by the plurality of SAR ADCs.

17. The IC of claim 12, wherein the cycle LSB signal has a sequence of discrete values over a plurality of SAR cycles, and wherein, for each of the plurality of SAR ADCs, the comparator is configured to perform a sequence of comparisons between the input signal and the constant reference voltage over the plurality of SAR cycles, the SAR logic is configured to generate a digital value based on the sequence of comparisons, and the reference input circuit is configured to successively adjust the input signal in response to the sequence of discrete values of the cycle LSB signal.

18. A method of converting a plurality of analog signals to a plurality of digital signals, the method comprising:

providing the plurality of analog signals to a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive a respective one of the plurality of analog signals, a second input that configured to receive a cycle LSB signal, and an output configured to provide a respective one of the plurality of digital signals; and

generating the cycle LSB signal using a cycle LSB reference generator shared by the plurality of SAR ADCs.

19. The method of claim 18, further comprising, for each of the plurality of SAR ADCs:

sampling a respective one of the plurality of analog signals to generate an input signal;

successively comparing the input signal with a constant reference voltage to generate a comparison result, and updating the input signal based on the comparison result and a value of the cycle LSB signal, for a plurality of SAR cycles; and

generating a digital code based on the comparison result of each of the plurality of SAR cycles.

20. The method of claim 18, further comprising, for each of the plurality of SAR ADCs:

sampling a respective one of the plurality of analog signals to generate a first input signal;

successively comparing the first input signal with a second input signal to generate a comparison result, and updating the second input signal based on the comparison result and a value of the reference signal, for a plurality of SAR cycles; and

generating a digital code based on the comparison result of each of the plurality of SAR cycles.

21. The method of claim 18, wherein the shared cycle LSB generator comprises a voltage source and the cycle LSB signal comprises a voltage signal or a current signal.

22. The method of claim 18, wherein the cycle LSB signal has a sequence of discrete values over a plurality of SAR cycles.

23. A method of converting a plurality of analog signals to a plurality of digital signals, the method comprising:

providing the plurality of analog signals to a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first capacitor that receives a respective one of the plurality of analog signals, a reference input circuit that receives a cycle LSB signal and is coupled to the first capacitor, and a comparator that is coupled to the first capacitor and provides a respective one of the plurality of digital signals; and

each of the SAR ADCs controlling a voltage at the first capacitor to be α

[k](V[k−

1]−

D[k−

1]·

LSB[k]), where D[k] is a voltage output from the comparator in a kth cycle, LSB[k] is a voltage of the cycle LSB signal in the kth cycle, α

[k] is a scale factor for the kth cycle, D[k−

1] is the voltage output from the comparator in a k−

1th cycle, and V[k−

1] is the voltage at the first capacitor at the k−

1th cycle.

24. The method of claim 23, wherein α

[k] has a sequence of discrete values over a plurality of SAR cycles, where α

[k] can assume values other than one and wherein α

[k] can vary from cycle to cycle.