Microfabricated ultrasonic transducers and related apparatus and methods

• US 10,228,353 B2
• Filed: 07/12/2017
• Issued: 03/12/2019
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Alie, Susan A., Fife, Keith G., Sanchez, Nevada J., Ralston, Tyler S.
• Primary Examiner(s): Kim, Su C
• Application Number:
  US15/648,187
• Publication Number:
  US 20170315099A1
• Time in Patent Office: 608 Days
• CPC Class Codes: A61B 8/4483 characterised by features of the ultrasound transducer
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/146 Mixed devices
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Claims

1. A method, comprising:

forming a layer of oxide on a first side of a first wafer, the first wafer having a second side opposite the first side;

forming a plurality of cavities in the layer of oxide;

bonding a second wafer with the first wafer such that the second wafer seals the plurality of cavities in the layer of oxide;

annealing the first wafer and the second wafer after bonding them together;

thinning the first wafer or the second wafer after the annealing to create a thinned wafer;

etching a plurality of trenches in the thinned wafer, the plurality of trenches defining a plurality of electrode regions of the thinned wafer;

filling the plurality of trenches with an insulating material;

forming metal contacts on the thinned wafer, at least some of the metal contacts corresponding to the plurality of electrode regions;

bonding the thinned wafer with a wafer having integrated circuitry formed therein using the metal contacts on the thinned wafer to contact bonding points on the wafer; and

thinning, after bonding the thinned wafer with the wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer.

2. The method of claim 1, wherein forming the plurality of cavities in the layer of oxide comprises etching completely through the layer of oxide.

3. A method for fabricating micromachined ultrasound transducers, comprising:

forming a plurality of cavities in a layer of oxide on a first side of a first wafer, the first wafer having a second side opposite the first side;

bonding a second wafer with the first wafer such that the second wafer seals the plurality of cavities in the layer of oxide;

annealing the first wafer and the second wafer after bonding them together the annealing utilizing a first temperature;

thinning the first wafer or the second wafer after the annealing to create a thinned wafer;

etching a plurality of trenches in the thinned wafer, the plurality of trenches defining a plurality of electrode regions of the thinned wafer;

filling the plurality of trenches in the thinned wafer with an insulating material;

forming metal contacts on the plurality of electrode regions of the thinned wafer;

aligning the thinned wafer with an integrated circuit wafer having integrated circuitry formed therein;

bonding the thinned wafer with the integrated circuit wafer having integrated circuitry formed therein using the metal contacts on the thinned wafer to contact bonding points on the integrated circuit wafer, wherein bonding the thinned wafer with the integrated circuit wafer is performed at a second temperature less than the first temperature; and

forming a flexible membrane by thinning, after bonding the thinned wafer with the integrated circuit wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer.