Hierarchical pre-fetch pipelining in a hybrid memory server

• US 10,228,863 B2
• Filed: 11/15/2017
• Issued: 03/12/2019
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuk Lung, Krishnamurthy, Rajaram B., Parris, Carl Joseph
• Primary Examiner(s): Bilgrami, Asghar H
• Application Number:
  US15/813,354
• Publication Number:
  US 20180074705A1
• Time in Patent Office: 482 Days
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 16/172 Caching, prefetching or hoarding of files
• CPC Class Codes: G06F 16/182 Distributed file systems
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2212/264 Remote server
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 41/5054 Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request.

Claims

1. A method, with an accelerator system in an out-of-core processing environment, comprising:

receiving, from a server comprising a memory system, an assignment of a first set of memory within the memory system that is to be managed by the accelerator system, where at least a second portion of memory within the memory system is managed by the server; and

writing data directly to the first set of memory at the server.

2. The method of claim 1, wherein the first set of memory is private to the accelerator system.

3. The method of claim of 1, wherein at least a third set of memory within the memory system is managed by at least one additional accelerator system.

4. The method of claim 3, further comprising:

transmitting a message to the additional accelerator system utilizing the first set of memory and the third set of memory.

5. The method of claim 1, wherein the first set of memory is communicatively coupled to the input-output bus of the server.

6. The method of claim 1, wherein the first set of memory is private to the accelerator system and one or more other portions of memory within the memory system are accessible by a plurality of accelerator systems.

7. The method of claim 1, further comprising:

receiving, from the server, a data set stored within at least one of the first set of memory and the second set of memory that is associated with the of accelerator system, wherein the data set has been transformed by the sever from a first format to a second format required by the accelerator system.

8. The method of claim 1, wherein the accelerator system comprises at least one gated memory, and where the method further comprises:

selectively allowing the server to access the at least one gate memory.

9. The method of claim 1, wherein the first set of memory comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, the method further comprising:

communicating at least one data set residing within the flash memory to another accelerator system over the input-output bus of the server, and wherein the accelerator system and the another accelerator system have direct access to the at least one flash memory module.

10. An accelerator system in an out-of-core processing environment comprising:

a memory;

a processing core communicatively coupled to the memory; and

a data manager communicatively coupled to the memory and the processing core, wherein the data manager is configured to perform a method comprising;

receiving, from a server comprising a memory system, an assignment of a first set of memory within the memory system that is to be managed by the accelerator system, where at least a second portion of memory within the memory system is managed by the server; and

writing data directly to the first set of memory at the server.

11. The accelerator system of claim 10, wherein the first set of memory is communicatively coupled to the input-output bus of the server.

12. The accelerator system of claim 10, wherein the method further comprises:

receiving, from the server, a data set stored within at least one of the first set of memory and the second set of memory that is associated with the accelerator system, wherein the data set has been transformed by the sever from a first format to a second format required by the accelerator system.

13. The accelerator system of claim 10, wherein the accelerator system further comprises:

at least one gated memory,

wherein the method further comprises;

selectively allowing the server to access the at least one gate memory.

14. The accelerator system of claim 10, wherein the first set of memory comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server,

wherein the method further comprises:

communicating at least one data set residing within the flash memory to another accelerator system over the input-output bus of the server, and wherein the accelerator system and the another accelerator system have direct access to the at least one flash memory module.

15. A computer program product for accessing data in an out-of-core processing environment, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit of an accelerator system in the out-of-core processing environment and storing instructions for execution by the processing circuit for performing a method comprising;

receiving, from a server comprising a memory system, an assignment of a first set of memory within the memory system that is to be managed by the accelerator system, where at least a second portion of memory within the memory system is managed by the server; and

writing data directly to the first set of memory at the server.

16. The computer program product of claim of 15, wherein at least a third set of memory within the memory system is managed by at least one additional accelerator system.

17. The computer program product of claim 15, wherein the first set of memory is communicatively coupled to the input-output bus of the server.

18. The computer program product of claim 15, wherein the method further comprises:

receiving, from the server, a data set stored within at least one of the first set of memory and the second set of memory that is associated with the accelerator system, wherein the data set has been transformed by the sever from a first format to a second format required by the accelerator system.

19. The computer program product of claim 15, wherein the accelerator system comprises at least one gated memory, and wherein the method further comprises

selectively allowing the server to access the at least one gate memory.

20. The computer program product of claim 15, wherein the first set of memory comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server,

wherein the method further comprises:

communicating at least one data set residing within the flash memory to another accelerator system over the input-output bus of the server, and wherein the accelerator system and the another accelerator system have direct access to the at least one flash memory module.