Method and system for low latency basket calculation

• US 10,229,453 B2
• Filed: 01/11/2008
• Issued: 03/12/2019
• Est. Priority Date: 01/11/2008
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Taylor, David E., Singla, Naveen, Brodie, Benjamin C., McVicar, Nathaniel Sutton, Thiel, Justin Ryan, Indeck, Ronald S.
• Primary Examiner(s): Pollock, Gregory A
• Application Number:
  US12/013,302
• Publication Number:
  US 20090182683A1
• Time in Patent Office: 4,078 Days
• Field of Search: 705 35, 705 36 R, 705 36 T, 705 37
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).

Claims

1. A method of processing data, the method comprising:

streaming financial market data through a field programmable gate array (FPGA), the financial market data comprising a plurality of messages that are associated with a plurality of financial instruments, wherein the messages comprise price information about the financial instruments, the FPGA having a pipeline deployed thereon, the pipeline including a first hardware module and a second hardware module, wherein the second hardware module is downstream from the first hardware module;

the first hardware module determining a plurality of financial instrument baskets which pertain to the financial instruments based on the messages;

the first hardware module writing a plurality of delta events to a delta event buffer in response to a plurality of the streaming financial market data messages, wherein each delta event comprises (1) data indicative of a basket determined by the first module, (2) data indicative of a price delta for the financial instrument pertaining to that determined basket, and (3) data indicative of a weight for that financial instrument within that determined basket;

the second hardware module reading the delta events from the delta event buffer;

the second hardware module computing a plurality of net asset values (NAVs) for the determined baskets with respect to the read delta events using a delta calculation approach that is based on a contribution of the price information for the financial instruments to the NAVs,

the second hardware module comprising;

a plurality of parallel computing paths, each computing path comprising NAV compute logic such that the computing paths are configured to simultaneously compute a plurality of different new NAVs for the determined baskets according to the delta calculation approach; and

wherein the second hardware module computing step comprises;

the second hardware module (1) accessing a plurality of memory tables that store a plurality of divisors and data values pertaining to old NAVs in association with a plurality of the baskets, and (2) retrieving divisors and data values pertaining to old NAVs from the memory tables for the determined baskets; and

the parallel computing paths simultaneously computing, via their respective NAV compute logic, a plurality of different new NAVs for the determined baskets according to the delta calculation approach using, for each determined basket, (1) the weight and price delta for the financial instrument pertaining to that determined basket, (2) the retrieved divisor for that determined basket, and (3) the retrieved data value pertaining to the old NAV for that determined basket; and

the first hardware module and the second hardware module operating together in a pipelined manner as the financial market data streams through the FPGA to perform the determining and computing steps simultaneously such that the determining step determines at least one financial instrument basket pertaining to a financial instrument represented by a message of the streaming financial market data while the computing step computes the new NAVs for a determined basket pertaining to a financial instrument represented by a previous message of the streaming financial market data.

2. The method of claim 1 wherein the data values pertaining to old NAVs comprise a plurality of old NAVs for the baskets.

3. The method of claim 1 wherein the data values pertaining to old NAVs comprise a plurality of S values for the baskets, wherein each S value represents a value corresponding to an old NAV for its associated basket multiplied by the divisor for that associated basket.

4. The method of claim 1 wherein the simultaneously computing step comprises the parallel NAV compute logic simultaneously computing a new bid NAV, a new ask NAV, and a new last NAV for the same basket using the delta calculation approach.

5. The method of claim 4 wherein the simultaneously computing step comprises the parallel NAV compute logic simultaneously computing the new bid NAV, the new ask NAV, the new last NAV, a new bid-tick NAV and a new ask+tick NAV for the same basket using the delta calculation approach.

6. The method of claim 1 further comprising:

a processor processing at least one of the computed new NAVs against a triggering condition to determine whether the at least one computed new NAV is to be reported to a client; and

generating a message for delivery to the client in response to a determination by the processing step that at least one of the computed new NAVs is to be reported to the client, the generated message comprising the at least one computed new NAV that is to be reported to the client.

7. The method of claim 6 wherein a third hardware module in the pipeline performs the processing step, further comprising the FPGA performing the first hardware module determining step, the second hardware module computing step, and the third hardware module processing step in a pipelined manner.

8. The method of claim 7 wherein a fourth hardware module in the pipeline performs the generating step, wherein the first module determining step, the second module computing step, the third hardware module processing step, and the fourth hardware module generating step are performed in a pipelined manner by the FPGA as the financial market data streams through the FPGA.

9. The method of claim 6 wherein the third hardware module processing step comprises:

the third hardware module retrieving a reference value for a basket from a first table based on a basket identifier associated with a computed new NAV;

the third hardware module determining a dissimilarity between the retrieved reference value and the computed new NAV;

the third hardware module retrieving a trigger threshold value for the basket from a second table based on the basket identifier; and

the third hardware module comparing the dissimilarity with the retrieved trigger threshold value to thereby determine whether the computed new NAV is to be reported to the client.

10. The method of claim 9 wherein the dissimilarity determining step comprises the third hardware module computing a difference between the retrieved reference value and the computed new NAV.

11. The method of claim 6 further comprising the third hardware module defining a plurality of triggering conditions for a plurality of baskets in response to input from the client.

12. The method of claim 1 further comprising a processor delivering the financial market data stream to the FPGA.

13. The method of claim 12 further comprising:

the processor filtering the messages prior to the first hardware module determining step based on at least one filtering criterion such that the first hardware module determining step is performed on the messages which pass the filtering step.

14. The method of claim 13 wherein the filtering step, the first hardware module determining step, and the second hardware module computing step are performed by the FPGA as the financial market data streams through the FPGA.

15. The method of claim 14 further comprising the FPGA performing the filtering step, the first hardware module determining step, and the second hardware module computing step in a pipelined manner.

16. The method of claim 12 further comprising:

a processor detecting an arbitrage condition in connection with a basket based on a computed new NAV for that basket; and

a processor placing at least one trade order with at least one financial market in response to the detecting step to thereby take advantage of the detected arbitrage condition.

17. The method of claim 16 wherein the pipeline comprises a third hardware module downstream from the second hardware module, the third hardware module performing the detecting step.

18. The method of claim 12 wherein each of at least a plurality of the messages comprises a symbol identifier and a global exchange identifier (GEID) corresponding to that message'"'"'s associated financial instrument, wherein the determining step comprises:

the first hardware module retrieving basket set data from a memory based on a message within the streaming financial market data using the symbol identifier and GEID within that message, the retrieved basket set data comprising at least one basket identifier for identifying a financial instrument basket having the financial instrument associated with that message as a member.

19. The method of claim 18 wherein the retrieved basket set data for at least one of the messages comprises a plurality of different basket identifiers, and wherein the computing step comprises the second hardware module performing the second hardware module computing step for each of the baskets identified by the basket identifiers.

20. The method of claim 19 wherein the delta calculation approach computes a new NAV for a basket as a function of the price delta pertaining to that basket, the retrieved divisor for that basket, a retrieved old NAV data value for that basket, and the weight assigned to the financial instrument for that basket, and wherein the basket set data retrieving step further comprises the first hardware module retrieving the weights for the baskets.

21. The method of claim 20 wherein each retrieved basket identifier is associated with a different one of the retrieved weights.

22. The method of claim 21 further comprising:

the first hardware module calculating a plurality of the price deltas for the financial instruments; and

first hardware module generating the delta events.

23. The method of claim 22 further comprising:

storing the basket identifiers and their associated weights in a table as plurality of pairs.

24. The method of claim 23 wherein the storing step further comprises storing previous price information for the financial instrument in the table.

25. The method of claim 24 further comprising updating the previous price information in the table based on the message.

26. The method of claim 23 wherein the table comprises a first table, wherein the storing step further comprises storing a plurality of pointers in a second table, the pointers being indexed by data corresponding to the symbol identifiers, and wherein the pairs in the first table are indexed by the pointers, and wherein the basket set data retrieving step further comprises the first hardware module (i) retrieving a pointer from the second table based on the message'"'"'s symbol identifier, and (ii) retrieving the pairs from the first table based on the retrieved pointer.

27. The method of claim 26 further comprising a processor adding and deleting basket definitions within the tables in response to input from a client.

28. The method of claim 26 further comprising the processor performing at least one of the group consisting of (i) adding a financial instrument to, (ii) modifying a weight for a financial instrument with respect to, and (iii) deleting a financial instrument from a basket by modifying the tables in response to input from a client.

29. The method of claim 19 wherein the basket set data retrieving step comprises the first hardware module retrieving data corresponding to a composite financial instrument and data corresponding to at least one regional financial instrument based each GEID.

30. The method of claim 12 wherein the processor comprises a general purpose processor (GPP).

31. The method of claim 30 wherein the processor comprises a plurality of the GPPs.

32. The method of claim 12 wherein the reconfigurable logic device FPGA performs the first module determining step and the second module computing step at hardware speeds.

33. The method of claim 1 further comprising the second hardware module performing the retrieving step and the simultaneously computing step in a pipelined manner such that the second hardware module performs the retrieving step for a delta event while the parallel computing paths are simultaneously performing the simultaneously computing steps for a previous delta event.

34. The method of claim 33 wherein the memory tables comprise (1) a first memory table that stores the divisors in association with a plurality of the basket identifiers, and (2) a plurality of second memory tables, each second memory table corresponding to a parallel computing path and configured to store a plurality of the data values pertaining to old NAVs in association with a plurality of a plurality of the basket identifiers;

and

wherein the retrieving step comprises (1) the second hardware module retrieving divisors for the determined baskets from the first memory table based on the basket identifiers in the read delta events, and (2) each parallel computing path retrieving the data values pertaining to old NAVs from its corresponding second memory table based on the basket identifiers in the read delta events.

35. The method of claim 1 wherein the stored data values pertaining to old NAVs comprise a plurality of old NAVs for the baskets.

36. The method of claim 35 wherein each respective NAV compute logic within the parallel computing paths comprises a multiplier, a divider downstream from the multiplier, and an adder downstream from the divider, and wherein the simultaneously computing step comprises, for each respective NAV compute logic with respect to each read delta event:

the multiplier multiplying the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the divider dividing the price delta-weight value product by the retrieved divisor for that delta event to thereby compute a delta contribution for that delta event; and

the adder adding the delta contribution for that delta event to the retrieved old NAV for that delta event to thereby compute a new NAV for that delta event; and

wherein the multiplier, divider, and adder operate together simultaneously in a pipelined manner.

37. The method of claim 36 wherein each respective NAV compute logic within the parallel computing paths consists of the multiplier, the divider, and the adder.

38. The method of claim 35 wherein each respective NAV compute logic within the parallel computing paths comprises a first multiplier, a second multiplier, an adder downstream from the first and second multipliers, and a divider downstream from the adder, and wherein the simultaneously computing step comprises, for each respective NAV compute logic with respect to each read delta event:

the first multiplier multiplying the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the second multiplier multiplying the retrieved old NAV for that delta event by the retrieved divisor for that delta event to thereby compute an S value for that delta event;

the adder adding the S value for that delta event to the price delta-weight value product for that delta event to thereby compute a sum value for that delta event; and

the divider dividing the sum value for that delta event by the retrieved divisor for that delta event to thereby compute a new NAV for that delta event; and

wherein the first multiplier and the second multiplier operate together simultaneously in a parallel manner; and

wherein the first and second multipliers, the adder, and the divider operate together simultaneously in a pipelined manner.

39. The method of claim 38 wherein each respective NAV compute logic within the parallel computing paths consists of the first multiplier, the second multiplier, the adder, and the divider.

40. The method of claim 1 wherein the stored data values pertaining to old NAVs comprise a plurality of S values for the baskets, each S value being representative of an old NAV for a basket multiplied by the divisor for that basket.

41. The method of claim 40 wherein each respective NAV compute logic within the parallel computing paths comprises a multiplier, an adder downstream from the multiplier, and a divider downstream from the adder, and wherein the simultaneously computing step comprises, for each respective NAV compute logic with respect to each read delta event:

the multiplier multiplying the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the adder adding the price delta-weight value product for that delta event and the retrieved S value for that delta event to thereby compute a sum value for that delta event; and

the divider dividing the sum value for that delta event by the retrieved divisor for that delta event to thereby compute a new NAV for that delta event; and

wherein the multiplier, adder, and divider operate together simultaneously in a pipelined manner.

42. The method of claim 41 wherein each respective NAV compute logic within the parallel computing paths consists of the multiplier, the adder, and the divider.

43. The method of claim 1 wherein the price delta for each delta event comprises a bid price delta, an ask price delta, and a last price delta, and wherein the simultaneously computing step comprises:

the parallel computing paths simultaneously computing, via their respective NAV compute logic, a new bid NAV, a new ask NAV, and a new last NAV, for each read delta event according to the delta calculation approach.

44. The method of claim 43 further comprising the second hardware module generating an output stream comprising the new bid NAV, the new ask NAV, the new last NAV, and a basket identifier for the each of the delta events.

45. The method of claim 1 wherein the parallel NAV compute logic is part of a NAV update engine within the second hardware module, and wherein the second hardware module further comprises a plurality of the NAV update engines in parallel, the method further comprising:

the plurality of NAV update engines operating in parallel on a plurality of the delta events to thereby simultaneously compute a plurality of the new NAVs from the plurality of delta events.

46. The method of claim 45 wherein the second hardware module further comprises routing logic upstream from the parallel NAV update engines, the method further comprising:

the second hardware module reading a plurality of the delta events out of the delta event buffer each clock cycle;

the routing logic (1) selecting, for each read delta event, one of the parallel NAV update engines, and (2) selectively routing the read delta events and the retrieved divisor values for the read delta events to the NAV update engines in accordance with the selecting step.

47. The method of claim 1 further comprising the second hardware module storing the new NAVs in the memory tables for use as old NAVs with respect to subsequent messages.

48. The method of claim 1 wherein the memory tables are resident on the FPGA.

49. The method of claim 1 wherein the memory tables are resident on a memory device in communication with the FPGA.

50. The method of claim 1 further comprising:

the first hardware module generating the delta events for the determined baskets.

51. The method of claim 50 wherein the first hardware module determining step comprises:

the first hardware module receiving a plurality of symbol identifiers and a plurality of global exchange identifiers (GEIDs) in association with the price information for a plurality of financial instruments, the symbol identifiers and GEIDs for identifying the financial instruments associated with the price information;

the first hardware module determining the plurality of baskets by retrieving a plurality of the basket identifiers from a basket memory based at least in part on the received symbol identifiers and GEIDs.

52. The method of claim 51 further comprising:

the first hardware module retrieving a plurality of the weights from the basket memory based at least in part on the received symbol identifiers and GEIDs, each weight being associated in the basket memory with a retrieved basket identifier.

53. The method of claim 52 further comprising:

the first hardware module retrieving price data from the basket memory based at least in part on the received symbol identifiers and GEIDs, the retrieved price data identifying a plurality of previous prices for the financial instruments identified by the symbol identifiers and the GEIDs; and

the first hardware module computing a plurality of the price deltas for the financial instruments identified by the symbol identifiers and the GEIDs by computing a plurality of differences between the retrieved price data and the received price information for those financial instruments.

54. The method of claim 51 wherein the basket memory comprises a basket set pointer table and a basket set table;

wherein the basket set table comprises the basket identifiers, the weights, and the price data; and

wherein the basket set pointer table comprises a plurality of pointers to portions of the basket set table, the pointers being associated with the received symbol identifiers and GEIDs.

55. The method of claim 51 wherein the basket memory is resident on the FPGA.

56. The method of claim 51 wherein the basket memory is resident on a memory device in communication with the FPGA.

57. The system of claim 1 wherein the basket association lookup hardware module and the basket value updating hardware module are configured to operate at hardware speeds.

58. The method of claim 1 wherein the price delta data comprises at least two members of the group consisting of (1) data indicative of a bid price delta for the financial instrument pertaining to that determined basket, (2) data indicative of an ask price delta for the financial instrument pertaining to that determined basket, and (3) data indicative of a last price delta for the financial instrument pertaining to that determined basket;

wherein the second hardware module further comprises a demultiplexer positioned between the delta event buffer and the parallel NAV compute logic; and

wherein the method further comprises the demultiplexer selectively routing the price delta data members to the parallel NAV compute logic for the parallel NAV compute logic to simultaneously compute the new NAVs corresponding to the price delta data members.

59. The method of claim 58 wherein the memory tables comprise (1) a first memory table that stores the divisors in association with a plurality of the basket identifiers, and (2) a plurality of second memory tables, each second memory table corresponding to a parallel computing path and configured to store a plurality of the data values pertaining to old NAVs in association with a plurality of a plurality of the basket identifiers;

and

wherein the retrieving step comprises (1) the second hardware module retrieving divisors for the determined baskets from the first memory table based on the basket identifiers in the read delta events, and (2) each parallel computing path retrieving the data values pertaining to old NAVs from its corresponding second memory table based on the basket identifiers in the read delta events.

60. A system for processing data, the system comprising:

a field programmable gate array (FPGA) for processing streaming financial market data, the streaming financial market data comprising a plurality of messages that are associated with a plurality of financial instruments, wherein the messages comprise price information about the financial instruments, the FPGA having a pipeline deployed thereon, the pipeline comprising a basket association lookup hardware module and a downstream basket value updating hardware module, the FPGA further comprising a delta event buffer; and

a memory accessible to the FPGA, wherein the memory comprises a plurality of memory tables that store a plurality of divisors and data values pertaining to a plurality of old net asset values (NAVs) in association with a plurality of financial instrument baskets;

the basket association lookup hardware module configured to (1) determine a plurality of financial instrument baskets which pertain to the financial instruments based on the messages, and (2) write a plurality of delta events to the delta event buffer in response to a plurality of the streaming financial market data messages, wherein each delta event comprises (1) data indicative of a basket determined by the basket association lookup module, (2) data indicative of a price delta for the financial instrument pertaining to that determined basket, and (3) data indicative of a weight for that financial instrument within that determined basket;

the basket value updating hardware module configured to (1) read the delta events from the delta event buffer, and (2) compute a plurality of NAVs for the determined baskets with respect to the read delta events using a delta calculation approach that is based on a contribution of the price information for the financial instruments to the NAVs, the basket value updating module hardware comprising;

a plurality of parallel computing paths, each computing path comprising NAV compute logic such that the computing paths are configured to simultaneously compute a plurality of different new NAVs for the determined baskets according to the delta calculation approach;

wherein the basket value updating hardware module is further configured to retrieve divisors and data values pertaining to old NAVs from the memory tables for the determined baskets; and

wherein the parallel computing paths are configured to simultaneously compute, via their respective NAV compute logic, a plurality of different new NAVs for the determined baskets according to the delta calculation approach using, for each determined basket, (1) the price delta for the financial instrument pertaining to that determined basket, (2) the retrieved divisor for that determined basket, and (3) the retrieved data value pertaining to old NAV for that determined basket; and

wherein the basket association lookup hardware module and the basket value updating hardware module are arranged in a pipelined manner such that the basket association lookup hardware module and the basket value updating hardware module are configured to operate simultaneously, wherein the basket association lookup hardware module is configured to determine a financial instrument basket pertaining to a financial instrument represented by a message of the streaming financial market data while the basket value updating hardware module is configured to compute the new NAVs for a determined basket pertaining to a financial instrument represented by a previous message of the streaming financial market data.

61. The system of claim 60 further comprising:

a processor configured to deliver the streaming financial market data stream to the FPGA.

62. The system of claim 61 wherein the parallel NAV compute logic are configured to simultaneously compute a new bid NAV, a new ask NAV, and a new last NAV for the same basket according to the delta calculation approach.

63. The system of claim 61 wherein the financial instrument associated with at least one of the messages is a member of a plurality of baskets, and wherein the basket value updating hardware module is further configured to compute the new NAVs for each of the baskets pertaining to that financial instrument.

64. The system of claim 63 wherein the basket value updating hardware module each respective NAV compute logic is further configured to compute its new NAV according to the delta calculation approach further using, for each determined basket, the weight for the financial instrument for each determined basket, and wherein the basket association lookup hardware module is further configured to retrieve the weights for the baskets.

65. The system of claim 64 wherein the basket association lookup hardware module is further configured to retrieve a basket identifier for each of the determined baskets, each basket identifier corresponding to a different one of the determined baskets and being associated with a different one of the weights.

66. The system of claim 65 wherein the message comprises a global exchange identifier, and wherein the basket association lookup hardware module is further configured to retrieve data corresponding to a composite financial instrument and data corresponding to at least one regional financial instrument based on the global exchange identifier.

67. The system of claim 61 wherein the FPGA further comprises a price event trigger hardware module in communication with the basket value updating hardware module, the price event trigger hardware module being configured to process a computed new NAV against a triggering condition to determine whether that computed new NAV is to be reported to a client.

68. The system of claim 67 wherein the basket association lookup hardware module, the basket value updating hardware module, and the price event trigger hardware module are arranged to operate in a pipelined manner on the FPGA.

69. The system of claim 68 wherein the FPGA further comprises an event generator hardware module in communication with the price event trigger hardware module, wherein the event generator hardware module is configured to generate a message for delivery to the client in response to a determination by the price event trigger hardware module that a computed new NAV is to be reported to the client, the generated message comprising that computed new NAV.

70. The system of claim 69 wherein the basket association lookup hardware module, the basket value updating hardware module, the price event trigger hardware module, and the event generator hardware module are arranged to operate in a pipelined manner on the FPGA.

71. The system of claim 67 wherein the price event trigger hardware module is further configured to:

retrieve a reference value for a basket from a first table based on a basket identifier associated with a computed new NAV;

determine a dissimilarity between the retrieved reference value and the computed new NAV;

retrieve a trigger threshold value for the basket from a second table based on the basket identifier; and

compare the dissimilarity with the retrieved trigger threshold value to thereby determine whether the computed new NAV is to be reported to the client.

72. The system of claim 61 wherein the financial market data comprises a plurality of messages, and wherein the FPGA further comprises a message qualifier filter in communication with the basket association lookup hardware module, the message qualifier filter being configured to filter the messages based on at least one filtering criterion such that the basket association lookup hardware module receives the messages which pass the message qualifier filter.

73. The system of claim 72 wherein the message qualifier filter, the basket association lookup hardware module, and the basket value updating hardware module are arranged to operate in a pipelined manner on the FPGA.

74. The system of claim 61 further comprising another processor in communication with the processor, wherein the another processor is configured to execute a client application, and wherein the processor is further configured to deliver data corresponding to the computed new NAVs to the client application.

75. The system of claim 61 wherein the processor comprises a general purpose processor (GPP).

76. The system of claim 75 wherein the processor comprises a plurality of the GPPs.

77. The system of claim 61 wherein the basket value updating hardware module is further configured to (1) read a plurality of the delta events from the delta event buffer, and (2) perform the retrieval operation and the simultaneous computation operations based on each of the read delta events.

78. The system of claim 77 wherein the basket value updating hardware module is further configured to perform the retrieval operation and the simultaneous computation operations in a pipelined manner such that the basket value updating hardware module is configured to perform the retrieval operation for a delta event while the parallel computing paths simultaneously perform the new NAV computations for a previous delta event.

79. The system of claim 78 the memory tables comprise (1) a first memory table that stores the divisors in association with a plurality of the basket identifiers, and (2) a plurality of second memory tables, each second memory table corresponding to a parallel computing path and configured to store a plurality of the data values pertaining to old NAVs in association with a plurality of a plurality of the basket identifiers;

and

wherein basket value updating hardware module is further configured to retrieve divisors for the determined baskets from the first memory table based on the basket identifiers in the read delta events; and

wherein each parallel computing path is further configured to retrieve the data values pertaining to old NAVs from its corresponding second memory table based on the basket identifiers in the read delta events.

80. The system of claim 79 wherein the stored data values pertaining to old NAVs comprise a plurality of S values for the baskets, each S value being representative of an old NAV for a basket multiplied by the divisor for that basket.

81. The system of claim 80 wherein each respective NAV compute logic within the parallel computing paths comprises a multiplier, an adder downstream from the multiplier, and a divider downstream from the adder;

the multiplier being configured to, for each delta event, multiply the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the adder being configured to, for each delta event, add the price delta-weight value product for that delta event and the retrieved S value for that delta event to thereby compute a sum value for that delta event; and

the divider being configured to, for each delta event, divide the sum value for that delta event by the retrieved divisor for that delta event to thereby compute a new NAV for that delta event; and

wherein the multiplier, adder, and divider are configured to operate together simultaneously in a pipelined manner.

82. The system of claim 81 wherein each respective NAV compute logic within the parallel computing paths consists of the multiplier, the adder, and the divider.

83. The system of claim 77 wherein the stored data values pertaining to old NAVs comprise a plurality of old NAVs for the baskets.

84. The system of claim 83 wherein each respective NAV compute logic within the parallel computing paths comprises a multiplier, a divider downstream from the multiplier, and an adder downstream from the divider;

the multiplier being configured to, for each delta event, multiply the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the divider being configured to, for each delta event, divide the price delta-weight value product by the retrieved divisor for that delta event to thereby compute a delta contribution for that delta event; and

the adder being configured to, for each delta event, add the delta contribution for that delta event to the retrieved old NAV for that delta event to thereby compute a new NAV for that delta event; and

wherein the multiplier, divider, and adder are configured to operate together simultaneously in a pipelined manner.

85. The system of claim 84 wherein each respective NAV compute logic within the parallel computing paths consists of the multiplier, the divider, and the adder.

86. The system of claim 83 wherein each respective NAV compute logic within the parallel computing paths comprises a first multiplier, a second multiplier, an adder downstream from the first and second multipliers, and a divider downstream from the adder;

the first multiplier being configured to, for each delta event, multiply the price delta for that delta event by the weight for that delta event to thereby compute a price delta-weight value product;

the second multiplier being configured to, for each delta event, multiply the retrieved old NAV for that delta event by the retrieved divisor for that delta event to thereby compute an S value for that delta event;

the adder being configured to, for each delta event, add the S value for that delta event to the price delta-weight value product for that delta event to thereby compute a sum value for that delta event; and

the divider being configured to, for each delta event, divide the sum value for that delta event by the retrieved divisor for that delta event to thereby compute a new NAV for that delta event; and

wherein the first multiplier and the second multiplier are configured to operate together simultaneously in a parallel manner; and

wherein the first and second multipliers, the adder, and the divider are configured to operate together simultaneously in a pipelined manner.

87. The system of claim 86 wherein each respective NAV compute logic within the parallel computing paths consists of the first multiplier, the second multiplier, the adder, and the divider.

88. The system of claim 77 wherein the price delta for each delta event comprises a bid price delta, an ask price delta, and a last price delta, and wherein the parallel computing paths are further configured to simultaneously compute, via their respective NAV compute logic components, a new bid NAV, a new ask NAV, and a new last NAV, for each read delta event according to the delta calculation approach.

89. The system of claim 88 wherein the basket value updating hardware module is further configured to generate an output stream comprising the new bid NAV, the new ask NAV, the new last NAV, and a basket identifier for the each of the delta events.

90. The system of claim 77 wherein the parallel NAV compute logic is part of a NAV update engine within the basket value updating hardware module, and wherein the basket value updating hardware module further comprises a plurality of the NAV update engines in parallel, the plurality of NAV update engines being configured to operate in parallel on a plurality of the delta events to thereby simultaneously compute a plurality of the new NAVs from the plurality of delta events.

91. The system of claim 90 wherein the basket value updating hardware module further comprises routing logic upstream from the parallel NAV update engines;

wherein the basket value updating hardware module is further configured to read a plurality of the delta events out of the delta event buffer each clock cycle; and

wherein the routing logic is configured to (1) select, for each read delta event, one of the parallel NAV update engines, and (2) selectively route the read delta events and the retrieved divisor values for the read delta events to the NAV update engines in accordance with the selection.

92. The system of claim 77 wherein the basket value updating hardware module is further configured to store the new NAVs in the memory tables for use as old NAVs with respect to subsequent messages.

93. The system of claim 77 wherein the memory is resident on the FPGA.

94. The system of claim 77 wherein the memory is resident on a memory device in communication with the FPGA.

95. The system of claim 77 wherein the basket association lookup hardware module is further configured to generate the delta events for the determined baskets.

96. The system of claim 95 wherein the basket association lookup hardware module is further configured to (1) receive a plurality of symbol identifiers and a plurality of global exchange identifiers (GEIDs) in association with the price information for a plurality of financial instruments, the symbol identifiers and GEIDs for identifying the financial instruments associated with the price information, and (2) determine the plurality of baskets by retrieving a plurality of the basket identifiers from a basket memory based at least in part on the received symbol identifiers and GEIDs.

97. The system of claim 96 wherein the basket association lookup hardware module is further configured to retrieve a plurality of the weights from the basket memory based at least in part on the received symbol identifiers and GEIDs, each weight being associated with a retrieved basket identifier.

98. The system of claim 97 wherein the basket association lookup hardware module is further configured to (1) retrieve price data from the basket memory based at least in part on the received symbol identifiers and GEIDs, the retrieved price data identifying a plurality of previous prices for the financial instruments identified by the symbol identifiers and the GEIDs, and (2) compute a plurality of the price deltas for the financial instruments identified by the symbol identifiers and the GEIDs by computing a plurality of differences between the retrieved price data and the received price information for those financial instruments.

99. The system of claim 96 wherein the basket memory comprises a basket set pointer table and a basket set table;

wherein the basket set table comprises the basket identifiers, the weights, and the price data; and

wherein the basket set pointer table comprises a plurality of pointers to portions of the basket set table, the pointers being associated with the received symbol identifiers and GEIDs.

100. The system of claim 96 wherein the basket memory is part of the memory, and wherein the memory is resident on the FPGA.

101. The system of claim 96 wherein the basket memory is part of the memory, and wherein the memory is resident on a memory device in communication with the FPGA.

102. The system of claim 60 wherein the price delta data comprises at least two members of the group consisting of (1) data indicative of a bid price delta for the financial instrument pertaining to that determined basket, (2) data indicative of an ask price delta for the financial instrument pertaining to that determined basket, and (3) data indicative of a last price delta for the financial instrument pertaining to that determined basket;

wherein the basket value updating hardware module further comprises a demultiplexer positioned between the delta event buffer and the parallel NAV compute logic, wherein the demultiplexer is configured to selectively route the price delta data members to the parallel NAV compute logic for the parallel NAV compute logic to simultaneously compute the new NAVs corresponding to the price delta data members.

103. The system of claim 102 wherein the memory tables comprise (1) a first memory table that stores the divisors in association with a plurality of the basket identifiers, and (2) a plurality of second memory tables, each second memory table corresponding to a parallel computing path and configured to store a plurality of the data values pertaining to old NAVs in association with a plurality of a plurality of the basket identifiers;

wherein the basket value updating hardware module is further configured to retrieve the divisors for the determined baskets from the first memory table based on the basket identifiers in the read delta events; and

wherein each parallel computing path is configured to retrieve the data values pertaining to old NAVs from its corresponding second memory table based on the basket identifiers in the read delta events.