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Mechanism to accelerate graphics workloads in a multi-core computing architecture

  • US 10,229,470 B2
  • Filed: 08/05/2016
  • Issued: 03/12/2019
  • Est. Priority Date: 08/05/2016
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a first processing core of a processor coupled to a an internal cache of the processor as a direct agent for thread instructions and data; and

    a second processing core of the processor coupled to the cache as a direct agent for separate thread instructions and data;

    a first programmable integrated circuit (IC) of the processor coupled to the first processing core to execute workloads assigned by the first processing core and coupled to the cache as a direct agent to access data of the first processing core independent of the first processing core to independently execute workloads;

    a second programmable IC of the processor coupled to the second processing core to execute workloads assigned by the second processing core and coupled to the cache as a direct agent to access data of the second processing core independent of the second processing core to independently execute workloads, wherein the first and second programmable ICs are field programmable gate arrays (FPGAs) that accelerate execution of performance critical loops in a workload; and

    a third processing core coupled to the first programmable IC, wherein the cache comprises a first memory device coupled only to the first processing core, the third processing core and the first programmable IC, and wherein the first programmable IC accelerates execution of workloads processed at the first processing core and the third processing core.

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