Block management for dynamic single-level cell buffers in storage devices

• US 10,229,735 B1
• Filed: 12/22/2017
• Issued: 03/12/2019
• Est. Priority Date: 12/22/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Natarajan, Shankar, Natarajan, Sriram, Nagarajan, Suresh, Ganesan, Ramkarthik, Athreya, Arun S., Trivedi, Romesh B.
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Radke, Jay
• Application Number:
  US15/852,928
• Time in Patent Office: 445 Days
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Claims

1. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

determine a programmable eviction ratio associated with a storage device,

convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio, wherein an amount of the portion converted into the multi-level cell region is to vary gradually as a function of percent capacity filled in the storage device,

detect one or more invalid blocks in the multi-level cell region,

determine a program mode of a pending write operation,

erase the one or more invalid blocks in accordance with the program mode, and

program the erased one or more invalid blocks in accordance with the program mode, wherein the program mode is to be either a single-level cell program mode or a multi-level cell program mode,

wherein when the storage device is in a runtime state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the runtime state, and wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

2. The semiconductor apparatus of claim 1, wherein when the storage device is in the runtime state, the portion converted into the multi-level cell region is to be from a dynamic single-level cell region.

3. The semiconductor apparatus of claim 1, wherein when the storage device is in the idle state, the portion converted into the multi-level cell region is to be from a static single-level cell region.

4. The semiconductor apparatus of claim 1, wherein when the storage device is in the idle state, the portion converted into the multi-level cell region is to be from a dynamic single-level cell region having a lower eviction priority than a static single-level cell region of the storage device.

5. A storage device comprising:

a power supply to provide power to the storage device;

a memory array including a single-level cell region and a multi-level cell region;

a memory controller including logic to;

determine a programmable eviction ratio associated with the storage device, and

convert a portion of the single-level cell region into the multi-level cell region in accordance with the programmable eviction ratio, wherein an amount of the portion converted into the multi-level cell region is to vary gradually as a function of percent capacity filled in the storage device.

6. The storage device of claim 5, wherein the memory controller is to:

detect one or more invalid blocks in the multi-level cell region,

determine a program mode of a pending write operation,

erase the one or more invalid blocks in accordance with the program mode, and

program the erased one or more invalid blocks in accordance with the program mode.

7. The storage device of claim 6, wherein the program mode is to be either a single-level cell program mode or a multi-level cell program mode.

8. The storage device of claim 5, wherein when the storage device is in a runtime state, the programmable eviction ratio is retrieved from a data structure dedicated to the runtime state and the single-level cell region is a dynamic single-level cell region.

9. The storage device of claim 5, wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

10. The storage device of claim 9, wherein the single-level cell region is a static single-level cell region.

11. The storage device of claim 9, wherein the single-level cell region is a dynamic single-level cell region having a lower eviction priority than a static single-level cell region of the storage device.

12. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

determine a programmable eviction ratio associated with a storage device, and

convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio, wherein an amount of the portion converted into the multi-level cell region is to vary gradually as a function of percent capacity filled in the storage device.

13. The semiconductor apparatus of claim 12, wherein the logic coupled to the one or more substrates is to:

detect one or more invalid blocks in the multi-level cell region,

determine a program mode of a pending write operation,

erase the one or more invalid blocks in accordance with the program mode, and

program the erased one or more invalid blocks in accordance with the program mode.

14. The semiconductor apparatus of claim 13, wherein the program mode is to be either a single-level cell program mode or a multi-level cell program mode.

15. The semiconductor apparatus of claim 12, wherein when the storage device is in a runtime state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the runtime state and the portion converted into the multi-level cell region is to be from a dynamic single-level cell region.

16. The semiconductor apparatus of claim 12, wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

17. The semiconductor apparatus of claim 16, wherein the portion converted into the multi-level cell region is to be from a static single-level cell region.

18. The semiconductor apparatus of claim 16, wherein the portion converted into the multi-level cell region is to be from a dynamic single-level cell region having a lower eviction priority than a static single-level cell region of the storage device.

19. A method comprising:

determining a programmable eviction ratio associated with a storage device comprising a memory controller; and

converting, using the memory controller, a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio, wherein an amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

20. The method of claim 19, further including:

detecting one or more invalid blocks in the multi-level cell region;

determining a program mode of a pending write operation;

erasing the one or more invalid blocks in accordance with the program mode; and

programming the erased one or more invalid blocks in accordance with the program mode.

21. The method of claim 20, wherein the program mode is either a single-level cell program mode or a multi-level cell program mode.

22. The method of claim 19, wherein when the storage device is in a runtime state, the programmable eviction ratio is retrieved from a data structure dedicated to the runtime state and the portion converted into the multi-level cell region is from a dynamic single-level cell region.

23. The method of claim 19, wherein when the storage device is in an idle state, the programmable eviction ratio is retrieved from a data structure dedicated to the idle state.

24. The method of claim 23, wherein the portion converted into the multi-level cell region is from a static single-level cell region.

25. The method of claim 23, wherein the portion converted into the multi-level cell region is from a dynamic single-level cell region having a lower eviction priority than a static single-level cell region of the storage device.