Power semiconductor device and package

• US 10,229,861 B2
• Filed: 04/06/2018
• Issued: 03/12/2019
• Est. Priority Date: 04/06/2017
• Status: Active Grant

• Current Assignee: Sabin Lupan
• Original Assignee: Sabin Lupan
• Inventors: Lupan, Sabin
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US15/947,756
• Publication Number:
  US 20180294204A1
• Time in Patent Office: 340 Days
• Field of Search: 257691, 257723, 257724, 257707
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/67 of a plurality of connectors
• CPC Class Codes: H01L 24/70 of a plurality of connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H02M 1/08 : Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Abstract

A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays from the package input to an output of a respective pair of devices to be shorter than a time and heat conductivity delay from the package input to an output of a subsequent pair of devices.

Claims

1. A power semiconductor device and package, comprising:

a plurality of electrically parallel semiconductor device legs configured to share a line-in and line-out source regions and share a drain region between two devices in each leg, wherein each leg is laterally staggered from each other leg to distribute thermal conductivity across the shared source regions; and

a plurality of jigsaw patterned lateral isolation trenches in a substrate of the device, the trenches configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs.

2. The power semiconductor device and package of claim 1, further comprising an integrated package including the substrate, a plurality of source, drain and gate terminals in conduction via a plurality of conductive clips.

3. The power semiconductor device and package of claim 1, further comprising thermally conductive vertical terminal projections configured to be received by spring loaded female receptacles.

4. The power semiconductor device and package of claim 1, wherein the substrate comprises a metal brazed metal to conductive ceramic to metal brazed metal sandwich including a silicon nitride.

5. The power semiconductor device and package of claim 1, further comprising a gate and source/drain control voltage generated external to the semiconductor device and package.

6. The power semiconductor device and package of claim 1, wherein a source portion of a semiconductor device leg is laterally adjacent a drain portion of another semiconductor device leg.

7. A power semiconductor device and package, comprising:

a first semiconductor pair of devices configured between a first and a second source region and configured to share a drain region wherein a source portion of the first pair of devices is laterally adjacent a drain portion of a second pair of devices,

wherein the first pair of devices is laid out laterally diagonal from the second pair of devices to distribute thermal conductivity relative to an input and an output of the device package; and

a plurality of stair case patterned lateral isolation trenches in a substrate of the package, the trenches configured to isolate the laterally diagonal source regions from a common drain region of the first and the second semiconductor pair of devices.

8. The power semiconductor device and package of claim 7, further comprising an integrated package including the substrate, a plurality of source, drain and gate terminals in conduction via a plurality of conductive clips.

9. The power semiconductor device and package of claim 7, further comprising thermally conductive vertical terminal projections configured to be received by spring loaded female receptacles.

10. The power semiconductor device and package of claim 7, wherein the substrate comprises a metal brazed metal to conductive ceramic to metal brazed metal sandwich including a silicon nitride.

11. The power semiconductor device and package of claim 7, further comprising a gate and source/drain control voltage generated external to the semiconductor device and package.

12. The power semiconductor device and package of claim 7, wherein a source portion of the second semiconductor pair of devices is laterally adjacent a drain portion of a third semiconductor pair of devices.

13. The power semiconductor device and package of claim 7, wherein a source portion of the second semiconductor pair of devices is electrically isolated from the drain portion of a third semiconductor pair of devices by a stair case channel in the substrate.

14. A power semiconductor device and package system, comprising:

a first semiconductor pair of devices configured between a first and a second source region and configured to share a drain region laterally adjacent to a source portion of a second pair of devices,

wherein the first pair of devices is laid out in a staggered pattern from the second pair of devices to distribute thermal conductivity relative to an input and an output of the device package; and

a plurality of stair case patterned lateral isolation trenches in a substrate of the package, the trenches configured to isolate a staggered source region from a common drain region of the first and the second semiconductor pair of devices.

15. The power semiconductor device and package of claim 14, wherein a time delay from the package input to an output of the first pair of devices is shorter than a time delay from the package input to an output of the second pair of devices.

16. The power semiconductor device and package of claim 14, wherein a time delay from the package input to an output of the second pair of devices is shorter than a time delay from the package input to an output of the third pair of devices.

17. The power semiconductor device and package of claim 14, wherein a heat conductivity delay from the package input to an output of the first pair of devices is shorter than a heat conductivity delay from the package input to an output of the second pair of devices.

18. The power semiconductor device and package of claim 14, wherein a heat conductivity delay from the package input to an output of the second pair of devices is shorter than a heat conductivity delay from the package input to an output of the third pair of devices.

19. The power semiconductor device and package of claim 14, wherein a source portion of the second semiconductor pair of devices is laterally adjacent a drain portion of a third semiconductor pair of devices.

20. The power semiconductor device and package of claim 14, wherein a source portion of the second semiconductor pair of devices is electrically isolated from the drain portion of a third semiconductor pair of devices by a stair case channel in the substrate.