Dual lead frame semiconductor package and method of manufacture

• US 10,229,893 B2
• Filed: 03/13/2017
• Issued: 03/12/2019
• Est. Priority Date: 09/09/2010
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Kuo, Frank, Belani, Suresh
• Primary Examiner(s): Dulka, John P.
• Application Number:
  US15/457,790
• Publication Number:
  US 20170271304A1
• Time in Patent Office: 729 Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37013 being non uniform along the connector
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/4103 Connectors having different sizes
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/34 : Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/36 : Structure, shape, material or disposition of the strap connectors prior to the connecting process
• CPC Class Codes: H01L 24/38 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Claims

1. A semiconductor package, comprising:

a substrate lead frame configured for mounting a first face of an integrated circuit chip, and further configured to couple a plurality of electrical signals of said integrated circuit chip to an exterior of said semiconductor package;

a clip lead frame comprising;

a first clip lead portion configured to couple a first conductive region of said integrated circuit chip to a first portion of said substrate lead frame; and

a second clip lead portion configured to couple a second conductive region of said integrated circuit chip to a second portion of said substrate lead frame,

wherein said substrate lead frame comprises the same material as said clip lead frame.

2. The semiconductor package of claim 1, wherein the first and second conductive regions of said integrated circuit chip are on an opposite face of said integrated circuit chip from said first face.

3. The semiconductor package of claim 1, wherein each of said first and second portions of said clip lead frame are non-planar.

4. The semiconductor package of claim 1, wherein said clip lead frame comprises the same material as said substrate lead frame.

5. The semiconductor package of claim 1, wherein said clip lead frame is free of gold.

6. The semiconductor package of claim 1, wherein said semiconductor package is free of wire bonds.

7. The semiconductor package of claim 1, wherein said first clip lead portion is configured to couple to a source contact of said integrated circuit chip, and said second clip lead portion is configured to couple to a gate contact of said integrated circuit chip.

8. A semiconductor package comprising:

an integrated circuit chip comprising first and second opposing faces,

wherein said first face is electrically and mechanically coupled to a substrate lead frame, and

wherein said substrate lead frame couples a plurality of electrical signals of said integrated circuit chip to an exterior of said semiconductor package;

a clip lead frame comprising;

a first clip lead portion coupling a first conductive region of said integrated circuit chip to a first portion of said substrate lead frame; and

a second clip lead portion coupling a second conductive region of said integrated circuit chip to a second portion of said substrate lead frame,

wherein said clip lead frame consists of metal.

9. The semiconductor package of claim 8, wherein the first and second conductive regions of said integrated circuit chip are on said second face of said integrated circuit chip.

10. The semiconductor package of claim 8, wherein said first portion of said clip lead frame is non-planar.

11. The semiconductor package of claim 8, wherein said clip lead frame comprises the same material as said substrate lead frame.

12. The semiconductor package of claim 8, wherein said clip lead frame is free of gold.

13. The semiconductor package of claim 8, wherein said semiconductor package is free of wire bonds.

14. The semiconductor package of claim 8, wherein said first clip lead portion is configured to couple to a source contact of said integrated circuit chip, and said second clip lead portion is configured to couple to a gate contact of said integrated circuit chip.

15. A clip lead frame comprising:

a single contiguous piece of electrically conductive material comprising;

a plurality of first clip lead portions configured to couple a first conductive region of an integrated circuit chip to a first portion of a substrate lead frame;

a plurality of second clip lead portions configured to couple a second conductive region of said integrated circuit chip to a second portion of said substrate lead frame; and

a plurality of clip lead frame extensions coupled to said plurality of first clip lead portions and further coupled to said plurality of second clip lead portions.

16. The clip lead frame of claim 15 wherein said clip lead frame is non-planar.

17. The clip lead frame of claim 15 comprising one or more larger physical areas for providing an area required by absorption.

18. The clip lead frame of claim 15 wherein each of said first clip lead portions comprises a first clip lead portion end configured for solder reflow bonding to said first conductive region.

19. The clip lead frame of claim 15 wherein each of said first clip lead portions comprises a second clip lead recess portion configured for solder reflow bonding to said substrate lead frame.

20. The clip lead frame of claim 15 wherein said clip lead frame is free of structures joining materials together.