Display device including oxide semiconductor layer

• US 10,229,904 B2
• Filed: 04/30/2015
• Issued: 03/12/2019
• Est. Priority Date: 09/19/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Komori, Shigeki, Uochi, Hideki, Futamura, Tomoya, Kasahara, Takahiro
• Primary Examiner(s): Nguyen, Lauren
• Application Number:
  US14/700,455
• Publication Number:
  US 20150236007A1
• Time in Patent Office: 1,412 Days
• CPC Class Codes: G02F 1/133 Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate electrode with the gate insulating layer located between the oxide semiconductor layer and the gate electrode;

a channel protective layer over the oxide semiconductor layer;

a source region over the oxide semiconductor layer;

a drain region over the oxide semiconductor layer;

a source electrode over the source region and the channel protective layer; and

a drain electrode over the drain region and the channel protective layer,

wherein the source region comprises an oxide semiconductor and comprises a nanocrystal,

wherein the drain region comprises an oxide semiconductor and comprises a nanocrystal, and

wherein the gate electrode is electrically connected to one of the source electrode and the drain electrode.

2. The semiconductor device according to claim 1,

wherein the nanocrystal of the source region has a size of 1 nm to 10 nm, and

wherein the nanocrystal of the drain region has a size of 1 nm to 10 nm.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 1,

wherein the source region comprises indium, gallium, and zinc, and

wherein the drain region comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 1, further comprising:

a pixel comprising a transistor;

a protective circuit comprising an element;

a scan line; and

a wiring,

wherein the transistor comprises a semiconductor layer comprising a channel formation region,

wherein the element comprises the gate electrode, the gate insulating layer, the oxide semiconductor layer, the channel protective layer, the source region, the drain region, the source electrode, and the drain electrode,

wherein the scan line is electrically connected to a gate of the transistor and a gate of the element and one of a source and a drain of the element, and

wherein the wiring is electrically connected to the other one of the source and the drain of the element.

6. The semiconductor device according to claim 5, further comprising:

a scan line driver circuit electrically connected to the pixel through the scan line.

7. The semiconductor device according to claim 1, further comprising:

a pixel comprising a transistor;

a protective circuit comprising a first element, a second element and a third element;

a scan line; and

a wiring,

wherein the transistor comprises a semiconductor layer comprising a channel formation region,

wherein the first element comprises the gate electrode, the gate insulating layer, the oxide semiconductor, layer, the channel protective layer, the source region, the drain region, the source electrode, and the drain electrode,

wherein the scan line is electrically connected to a gate of the transistor, a gate of the first element, one of a source and a drain of the first element, and one of a source and a drain of the third element,

wherein the wiring is electrically connected to a gate of the second element, one of a source and a drain of the second element, and the other one of the source and the drain of the third element, and

wherein a gate of the third element is electrically connected to the other one of the source and the drain of the first element, and the other one of the source and the drain of the second element.

8. The semiconductor device according to claim 7, further comprising:

a scan line driver circuit electrically connected to the pixel through the scan line.

9. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate electrode with the gate insulating layer located between the oxide semiconductor layer and the gate electrode;

a channel protective layer over the oxide semiconductor layer;

a source electrode over the channel protective layer;

a drain electrode over the channel protective layer;

a source region located between the oxide semiconductor layer and the source electrode, the source region comprising an oxide semiconductor;

a drain region located between the oxide semiconductor layer and the drain electrode, the drain region comprising an oxide semiconductor,

wherein the source region comprises a nanocrystal,

wherein the drain region comprises a nanocrystal, and

wherein the gate electrode is electrically connected to one of the source electrode and the drain electrode.

10. The semiconductor device according to claim 9,

wherein the nanocrystal of the source region has a size of 1 nm to 10 nm, and

wherein the nanocrystal of the drain region has a size of 1 nm to 10 nm.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

12. The semiconductor device according to claim 9,

wherein the source region comprises indium, gallium, and zinc, and

wherein the drain region comprises indium, gallium, and zinc.

13. The semiconductor device according to claim 9, further comprising:

a pixel comprising a transistor;

a protective circuit comprising an element;

a scan line; and

a wiring,

wherein the transistor comprises a semiconductor layer comprising a channel formation region,

wherein the element comprises the gate electrode, the gate insulating layer, the oxide semiconductor layer, the channel protective layer, the source region, the drain region, the source electrode, and the drain electrode,

wherein the scan line is electrically connected to a gate of the transistor and a gate of the element and one of a source and a drain of the element, and

wherein the wiring is electrically connected to the other one of the source and the drain of the element.

14. The semiconductor device according to claim 13, further comprising:

a scan line driver circuit electrically connected to the pixel through the scan line.

15. The semiconductor device according to claim 9, further comprising:

a pixel comprising a transistor;

a protective circuit comprising a first element, a second element and a third element;

a scan line; and

a wiring,

wherein the transistor comprises a semiconductor layer comprising a channel formation region,

wherein the first element comprises the gate electrode, the gate insulating layer, the oxide semiconductor layer, the channel protective layer, the source region, the drain region, the source electrode, and the drain electrode,

wherein the scan line is electrically connected to a gate of the transistor, a gate of the first element, one of a source and a drain of the first element, and one of a source and a drain of the third element,

wherein the wiring is electrically connected to a gate of the second element, one of a source and a drain of the second element, and the other one of the source and the drain of the third element, and

wherein a gate of the third element is electrically connected to the other one of the source and the drain of the first element, and the other one of the source and the drain of the second element.

16. The semiconductor device according to claim 15, further comprising:

a scan line driver circuit electrically connected to the pixel through the scan line.