Adaptive charge balanced edge termination

• US 10,229,988 B2
• Filed: 12/11/2017
• Issued: 03/12/2019
• Est. Priority Date: 05/30/2012
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Tipirneni, Naveen, Pattanayak, Deva N.
• Primary Examiner(s): Gebremariam, Samuel
• Application Number:
  US15/838,165
• Publication Number:
  US 20180114852A1
• Time in Patent Office: 456 Days
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

Claims

1. A method comprising:

generating a junction extension region within an upper surface of an epitaxial layer of a semiconductor device, wherein said epitaxial layer comprising a first type dopant and said junction extension region comprising a second type dopant;

generating a field ring within said junction extension region and comprising a higher concentration of said second type dopant than said junction extension region; and

forming a field plate above and in physical contact with said field ring, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region,

wherein an edge termination of said semiconductor device comprises said junction extension region, said field ring, and said field plate.

2. The method of claim 1, further comprising:

forming a plurality of metal field plates, said edge termination comprises said plurality of metal field plates.

3. The method of claim 1, further comprising:

forming a plurality of polysilicon field plates, said edge termination comprises said plurality of polysilicon field plates.

4. The method of claim 1, wherein said junction extension region comprises laterally varying doping of said second type dopant.

5. The method of claim 1, wherein said field plate is in ohmic contact with said junction extension region.

6. The method of claim 1, further comprising:

forming a tub region within said epitaxial layer and comprising said second type dopant.

7. The method of claim 1, further comprising:

generating a plurality of field rings within said junction extension region, each of said plurality of field rings comprising a higher concentration of said second type dopant than said junction extension region, said edge termination comprises said plurality of field rings.

8. A method comprising:

generating a junction extension region within an upper surface of an epitaxial layer of a metal oxide semiconductor field effect transistor (MOSFET) device, wherein said epitaxial layer comprising a first type dopant and said junction extension region comprising a second type dopant;

generating a plurality of field rings within said junction extension region, each of said plurality of field rings comprising a higher concentration of said second type dopant than said junction extension region; and

forming a plurality of field plates, a field plate of said plurality of field plates is above and in physical contact with a field ring of said plurality of field rings, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region,

wherein an edge termination of said MOSFET device comprises said junction extension region, said plurality of field rings, and said plurality of field plates.

9. The method of claim 8, wherein each of said plurality of field plates comprises metal.

10. The method of claim 8, wherein each of said plurality of field plates comprises polysilicon.

11. The method of claim 8, wherein said junction extension region comprises laterally varying doping of said second type dopant.

12. The method of claim 8, further comprising:

forming a tub region within said epitaxial layer and comprising said second type dopant.

13. The method of claim 12, wherein said tub region in contact with and laterally adjacent to said junction extension region and extends deeper than said junction extension region.

14. The method of claim 8, wherein a second field plate of said plurality of field plates is above and in physical contact with a second field ring of said plurality of field rings.

15. A method comprising:

generating a junction extension region within an upper surface of an epitaxial layer of a semiconductor device, wherein said epitaxial layer comprising a first type dopant and said junction extension region comprising a second type dopant, said junction extension region comprises laterally varying doping of said second type dopant;

forming a tub region within said epitaxial layer and comprising said second type dopant;

generating a field ring within said junction extension region and comprising a higher concentration of said second type dopant than said junction extension region; and

forming a field plate above and in physical contact with said field ring, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region,

wherein an edge termination of said semiconductor device comprises said junction extension region, said field ring, and said field plate.

16. The method of claim 15, further comprising:

forming a plurality of metal field plates, said edge termination comprises said plurality of metal field plates.

17. The method of claim 15, further comprising:

forming a plurality of polysilicon field plates, said edge termination comprises said plurality of polysilicon field plates.

18. The method of claim 15, wherein said field plate is in ohmic contact with said junction extension region.

19. The method of claim 15, further comprising:

forming a plurality of field rings within said junction extension region and each comprising a higher concentration of said second type dopant than said junction extension region.

20. The method of claim 15, wherein said tub region contacts said junction extension region and extends deeper than said junction extension region.