Semiconductor device and method of manufacturing the same

• US 10,229,998 B2
• Filed: 03/07/2018
• Issued: 03/12/2019
• Est. Priority Date: 05/18/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Mihara, Tatsuyoshi
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Withers, Grant
• Application Number:
  US15/914,837
• Publication Number:
  US 20180337281A1
• Time in Patent Office: 370 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Variations in height of a top of an element isolation region, which is embedded in a trench surrounding the periphery of a fin having a channel region of a split-gate MONOS memory, are suppressed to improve reliability of a semiconductor device. An element isolation region embedded in a trench between a plurality of fins, which are part of a semiconductor substrate in a memory cell region and protrude above the semiconductor substrate, is comprised of an insulating film covering the bottom of the trench and a silicon nitride film covering the top of the insulating film.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first region and a second region arranged along a main surface of the semiconductor substrate;

a plurality of first protrusions that are a part of the semiconductor substrate in the first region, protrude from a top of the semiconductor substrate, and extend in a first direction along the main surface of the semiconductor substrate;

a first element isolation region embedded in a first trench between the first protrusions adjacent to each other;

a first gate electrode that is formed over tops of the first protrusions with a first insulating film in between, and extends in a second direction orthogonal to the first direction;

a second gate electrode that is formed over tops of the first protrusions with a second insulating film including a charge storage part in between, and extends in the second direction alongside the first gate electrode;

a first source-and-drain region formed in each of the tops of the first protrusions;

a plurality of second protrusions that are a part of the semiconductor substrate in the second region, protrude from the top of the semiconductor substrate, and extend in the first direction;

a second element isolation region embedded in a second trench between the second protrusions adjacent to each other,

a transistor including a third gate electrode that is formed over the tops of the second protrusions with a third insulating film in between and extends in the second direction, and a second source-and-drain region formed in each of the tops of the second protrusions,

wherein the first gate electrode and the second gate electrode extend directly over the first element isolation region,

wherein the first gate electrode, the second gate electrode, and the first source-and-drain region configure a nonvolatile memory element; and

wherein a top of the first element isolation region is configured by a top of a silicon nitride film and a top surface of a first silicon oxide film, and

wherein a top of the second element isolation region is configured entirely by a top of a second silicon oxide film.

2. The semiconductor device according to claim 1, wherein the first element isolation region includes:

a third silicon oxide film embedded in the first trench; and

the silicon nitride film formed over the third silicon oxide film.

3. The semiconductor device according to claim 1, wherein the first element isolation region further includes the first silicon oxide film formed between each of the first protrusions and the silicon nitride film.

4. The semiconductor device according to claim 3, wherein the top of the first element isolation region includes the top of the silicon nitride film and the top surface of the first silicon oxide film, and an area of the top of the silicon nitride film is larger than an area of the top surface of the first silicon oxide film.

5. The semiconductor device according to claim 1, wherein the silicon nitride film has a thickness of 5 nm to 15 nm.

6. The semiconductor device according to claim 1, further comprising a sidewall including a fourth insulating film that covers side surfaces on both sides of a pattern including the first gate electrode and the second gate electrode, and extends in the second direction.