Optical die test interface with separate voltages for adjacent electrodes

• US 10,230,458 B2
• Filed: 06/10/2013
• Issued: 03/12/2019
• Est. Priority Date: 06/10/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: McShane, Michael B., Pelley, Perry H., Stephens, Tab A.
• Primary Examiner(s): Jordan, Andrew
• Application Number:
  US13/914,199
• Publication Number:
  US 20140363153A1
• Time in Patent Office: 2,101 Days
• Field of Search: None
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H04B 10/07 Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems

Abstract

An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).

Claims

1. A method comprising:

providing a wafer comprising a first die and a scribe grid surrounding the first die,

the first die comprising a first optical waveguide beam located in a first structure at a peripheral die edge of the first die and surrounded by a plurality of separate deflection electrodes which are positioned to exert two-dimensional deflection of the first optical waveguide beam and which comprise first and second separate lateral deflection electrodes positioned on a first side of the first optical waveguide beam and separately connected to different, independently controlled voltages, and

the scribe grid comprising an optical deflection mirror for perpendicularly deflecting optical signals located in a second structure proximate to the peripheral die edge of the first die;

forming a recess opening in the scribe grid of the wafer to reveal or release at least the first optical waveguide beam at the peripheral die edge of the first die; and

performing one or more optical wafer die tests on the first die using at least a first optical signal that is received in a first plane that is perpendicular to a lateral plane of the wafer and perpendicularly deflected at the optical deflection mirror into the lateral plane of the wafer for transmission across the recess opening for reception at the first optical waveguide beam.

2. The method of claim 1, where providing the wafer comprises fabricating a plurality of integrated circuit die, each surrounded by a scribe grid, where the first optical waveguide beam is formed as a first deflectable cantilevered silicon beam surrounded by a first plurality of separate vertical deflection electrodes positioned above the first deflectable cantilevered silicon beam, a second plurality of separate vertical deflection electrodes positioned below the first deflectable cantilevered silicon beam, a third plurality of separate lateral deflection electrodes positioned on the first side of the first deflectable cantilevered silicon beam, and a fourth plurality of separate lateral deflection electrodes positioned on a second opposite side of the first deflectable cantilevered silicon beam, where the first deflectable cantilevered silicon beam is oriented for optical communication with optical deflection mirror.

3. The method of claim 1, where the optical deflection mirror comprises an angled interface deflection surface that is offset by 45 degrees from the lateral plane of the wafer.

4. The method of claim 1, where forming the recess opening comprises partially sawing through the wafer in the scribe grid to form a recess opening adjacent to the peripheral die edge of the first die which substantially reveals at least a distal end of the first optical waveguide beam.

5. The method of claim 1, where performing one or more optical wafer die tests comprises performing electrical open and short tests or light beam transfer tests on the first die.

6. The method of claim 1, where performing one or more optical wafer die tests comprises:

deflecting the first optical waveguide beam by a controlled deflection value through application of different, independently controlled voltages to each of the plurality of separate deflection electrodes and then measuring attenuation of the first optical signal as a function of the controlled deflection value.

7. The method of claim 1, where forming the recess opening comprises removing at least the first structure to release the first optical waveguide beam for cantilevered movement within the first die.

8. The method of claim 7, where performing one or more optical wafer die tests comprises performing one or more tests on the first die after removing at least the first structure to release the first optical waveguide beam for cantilevered movement within the first die.

9. The method of claim 8, further comprising filling at least part of the recess opening with a stabilizing material prior to singulation to stabilize the first optical waveguide beam against movement during singulation.

10. The method of claim 1, further comprising singulating the first die from the wafer by cutting through the scribe grid.

11. The method of claim 10, where singulating the first die from the wafer comprises performing a full saw cut through the scribe grid.

12. The method of claim 11, further comprising removing any remaining stabilizing material from around the first optical waveguide beam after singulation.

13. The method of claim 1, further comprising:

singulating the first die from the wafer after performing one or more optical wafer die tests; and

packaging the first die in a packaging structure.

14. A method for making an integrated circuit device comprising:

providing a first die that is surrounded by a first scribe grid while in wafer form, the first die comprising a first optical waveguide beam located at a peripheral die edge of the first die that is surrounded by a plurality of separate deflection electrodes which are positioned to exert two-dimensional deflection of the first optical waveguide beam and which comprise first and second separate lateral deflection electrodes positioned on a first side of the first optical waveguide beam and separately connected to different, independently controlled voltages; and

performing one or more optical wafer die probe tests on the first die while in wafer form after forming a recess opening in the scribe grid of the wafer to reveal or release the first optical waveguide beam;

where the first scribe grid comprises an optical deflection mirror located proximate to the peripheral die edge of the first die for perpendicularly deflecting optical signals to and/or from the first optical waveguide beam, and

where the one or more optical wafer die probe tests are performed on the first die by using an optical test signal that is received in a first plane that is perpendicular to a lateral plane of the first die and that is perpendicularly deflected at the optical deflection mirror into the lateral plane of the first die for reception at the first optical waveguide beam for use in optical testing of optical circuit elements in the first die.

15. The method of claim 14, where providing the first die comprises fabricating a plurality of integrated circuit die, each surrounded by a scribe grid, where the first optical waveguide beam is formed as a first deflectable cantilevered silicon beam oriented for optical communication with a corresponding optical deflection mirror located in a surrounding scribe grid, where the first deflectable cantilevered silicon beam extends into a first deflection cavity located at a peripheral die edge of the first die and which is at least partially filled with a first stabilization structure.

16. The method of claim 14, where forming the recess opening in the scribe grid of the wafer comprises partially sawing through the wafer to substantially reveal a distal end of the first optical waveguide beam.

17. The method of claim 16, where forming the recess opening comprises removing a stabilization structure with an etch process to release the first optical waveguide beam for cantilevered movement within the first die.

18. The method of claim 17, where the one or more optical wafer die probe tests are performed on the first die by performing one or more tests on the first die after removing the stabilization structure to release the first optical waveguide beam for cantilevered movement within the first die.

19. A semiconductor wafer comprising a plurality of scribe street regions surrounding a corresponding plurality of die, where each die comprises optical circuit elements and a deflectable optical waveguide beam located at a peripheral die edge of said die and surrounded by a plurality of separate deflection electrodes which are positioned to exert two-dimensional deflection of the optical waveguide beam, and which comprise first and second separate lateral deflection electrodes positioned on a first side of the deflectable optical waveguide beam and separately connected to different, independently controlled voltages, and where each scribe street region surrounding a die comprises a scribe street optical deflection mirror for receiving optical signals in a first plane that is perpendicular to a lateral plane of the wafer and for perpendicularly deflecting the received optical signals for optical communication through the deflectable optical waveguide beam for use in optical testing of the optical circuit elements.

20. The semiconductor wafer of claim 19, where the deflectable optical waveguide beam comprises a deflectable cantilevered silicon beam and where the plurality of separate deflection electrodes comprises a first plurality of separate vertical deflection electrodes positioned above the deflectable cantilevered silicon beam which are each independently controlled with different voltages, a second plurality of separate vertical deflection electrodes positioned below the deflectable cantilevered silicon beam, a third plurality of separate lateral deflection electrodes positioned on the first side of the deflectable cantilevered silicon beam, and a fourth plurality of separate lateral deflection electrodes positioned on a second opposite side of the first deflectable cantilevered silicon beam.