Detector remodulator and optoelectronic switch

• US 10,231,038 B2
• Filed: 02/24/2015
• Issued: 03/12/2019
• Est. Priority Date: 02/24/2014
• Status: Active Grant

• Current Assignee: Rockley Photonics Limited
• Original Assignee: Rockley Photonics Limited
• Inventors: Rickman, Andrew, Zilkie, Aaron
• Primary Examiner(s): Liu, Li
• Application Number:
  US15/120,861
• Publication Number:
  US 20170078772A1
• Time in Patent Office: 1,477 Days
• Field of Search: 398173-181
• CPC Class Codes: G02B 6/12019 characterised by the optical interconnection to or from the AWG devices, e.g. integration or coupling with lasers or photodiodes coupling integrated waveguide to fibre G02B6/30, to optoelectronic element G02B6/42; monolithic integration of integrated waveguides with other optical elements G02B6/12004
• CPC Class Codes: G02B 6/12021 Comprising cascaded AWG devices; AWG multipass configuration; Plural AWG devices integrated on a single chip
• CPC Class Codes: G02F 1/0157 using electro-absorption effects, e.g. Franz-Keldysh [FK] effect or quantum confined stark effect [QCSE]
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: G02F 1/212 Mach-Zehnder type
• CPC Class Codes: G02F 1/213 Fabry-Perot type
• CPC Class Codes: G02F 1/2257 the optical waveguides being made of semiconducting material
• CPC Class Codes: G02F 2203/15 involving resonance effects, e.g. resonantly enhanced interaction
• CPC Class Codes: H04B 10/29 Repeaters
• CPC Class Codes: H04B 10/505 using external modulation
• CPC Class Codes: H04J 14/02 Wavelength-division multiplex systems
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 11/0071 Provisions for the electrical-optical layer interface
• CPC Class Codes: H04Q 2011/0011 using wavelength conversion
• CPC Class Codes: H04Q 2011/0016 using wavelength multiplexing or demultiplexing
• CPC Class Codes: H04Q 2011/0018 using tunable transmitters or receivers
• CPC Class Codes: H04Q 2011/0032 using static wavelength routers (e.g. arrayed waveguide grating router [AWGR] )
• CPC Class Codes: H04Q 2011/0039 Electrical control

Abstract

A silicon-on-insulator chip including an arrayed waveguide grating (AWG) and an array of detector remodulators (DRMs) in a planar arrangement with the AWG such that the modulators or modulators and detectors of said DRMs are located within the same plane as the waveguides of the AWG; and wherein each DRM is located at an input or output of the AWG.

Claims

1. A silicon-on-insulator chip comprising:

a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and

a first array of detector remodulators (DRMs),

each of the DRMs comprising;

a detector;

a modulator; and

a CMOS circuit connected in cascade between the detector and the modulator,

the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a modulation waveguide region at which a second semiconductor junction is set horizontally across the modulation waveguide region in that the second semiconductor junction comprises a first doped region of the modulation waveguide region and a second doped region of the modulation waveguide region which is on an opposite side of the modulation waveguide region to the first doped region in a horizontal direction;

the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and

wherein each DRM is located at an input or output of the AWG,

wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.

2. The silicon-on-insulator chip of claim 1, wherein the detectors of the DRMs are located within the plane.

3. The silicon-on-insulator chip of claim 1, wherein a respective DRM of the first array of DRMs is located at each of one or more inputs of the first AWG and at each of one or more outputs of the first AWG.

4. The silicon-on-insulator chip of claim 3, wherein a respective DRM of the first array of DRMs is located at each input of the first AWG and at each output of the first AWG.

5. The silicon-on-insulator chip of claim 3, wherein a signal input waveguide for one or more of the DRMs lies within the plane.

6. The silicon-on-insulator chip of claim 3, wherein a signal input waveguide for one or more of the DRMs impinges the modulator of the DRM from an angle to the plane.

7. A system comprising:

the silicon-on-insulator chip of claim 1; and

one or more tunable lasers,

each tunable laser being for providing a wavelength tuned laser input to the modulator of a respective one or more of the DRMs.

8. The system of claim 7, wherein the one or more tunable lasers are located on the silicon-on-insulator chip.

9. The system of claim 8, wherein the one or more tunable lasers are located within the plane.

10. The system of claim 7, wherein a tunable laser of the one or more tunable lasers is thermally isolated from the first AWG and the DRMs.

11. The system of claim 7, wherein the one or more tunable lasers lies within the plane.

12. The system of claim 7, wherein:

a respective DRM of the first array of DRMs; and

a respective tunable laser, of the one or more tunable lasers,

are located at each input of the first AWG, the tunable laser being configured to provide the wavelength tuned laser input for the modulator of the DRM.

13. The system of claim 7, wherein:

a respective DRM of the first array of DRMs; and

a respective tunable laser, of the one or more tunable lasers,

are located at each output of the first AWG, the tunable laser being configured to provide the wavelength tuned laser input for the modulator of the DRM.

14. The silicon-on-insulator chip of claim 1, wherein:

the first AWG has a plurality of inputs and a plurality of outputs;

each of the first array of DRMs being located at a respective input of the first AWG, each DRM of the first array of DRMs being configured to receive a wavelength tunable laser input;

the first array of DRMs being arranged such that an output of each DRM of the first array of DRMs is configured to form an input signal for the first AWG;

the silicon-on-insulator chip further comprising;

a second AWG having a plurality of inputs and a plurality of outputs; and

a second array of DRMs, each located at a respective input to the second AWG;

each DRM of the second array of DRMs being configured to receive a wavelength tunable laser input;

the second array of DRMs being arranged such that an output of each DRM of the second array of DRMs is configured to form an input signal for the second AWG;

wherein each output of the first AWG is configured to form an input signal for a respective DRM of the second array of DRMs, and wherein;

the DRMs of the first array of DRMs,

the second AWG, and

the DRMs of the second array of DRMs

are in the plane.

15. The silicon-on-insulator chip of claim 14, wherein the first and second AWGs are located in an end-to-end arrangement on the silicon-on-insulator chip.

16. The silicon-on-insulator chip of claim 15, wherein the first and second AWGs are positioned in a nested arrangement within the plane.

17. The silicon-on-insulator chip of claim 1, wherein:

each DRM of the first array of DRMs is located at an input waveguide of the first AWG, and each DRM of the first array of DRMs is coupled to a tunable laser which is configured to provide a wavelength tuned input for the modulator of the DRM;

the silicon-on-insulator chip further comprising;

a second array of DRMs;

each DRM of the second array of DRMs being located at an output waveguide of the first AWG and each DRM of the second array of DRMs being coupled to a tunable laser which is configured to provide a wavelength tuned input for the modulator of the DRM;

an optical demultiplexer, an output of which is configured to form input signals for the first array of DRMs; and

an optical multiplexer, the inputs for which are the outputs of the second array of DRMs.

18. A silicon-on-insulator chip comprising:

a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and

a first array of detector remodulators (DRMs),

each of the DRMs comprising;

a detector;

a modulator; and

a CMOS circuit connected between the detector and the modulator,

the CMOS circuit having;

a first external contact connected to the detector and not connected to the modulator, and

a second external contact connected to the modulator and not connected to the detector,

the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a second semiconductor junction arranged in the plane;

the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and

wherein each DRM is located at an input or output of the AWG,

wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.

19. A silicon-on-insulator chip comprising:

a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and

a first array of detector remodulators (DRMs),

each of the DRMs comprising;

a detector;

a modulator; and

a CMOS circuit connected between the detector and the modulator,

the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a second semiconductor junction arranged in the plane;

wherein an output of the detector is connected to an input of the CMOS circuit and an output of the CMOS circuit is connected to an input of the modulator;

the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and

wherein each DRM is located at an input or output of the AWG,

wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.