Analog-to-digital drive circuitry having built-in time gain compensation functionality for ultrasound applications

• US 10,231,713 B2
• Filed: 09/13/2016
• Issued: 03/19/2019
• Est. Priority Date: 09/13/2016
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Chen, Kailiang, Fife, Keith G.
• Primary Examiner(s): Pihulic, Daniel
• Application Number:
  US15/263,939
• Publication Number:
  US 20180070925A1
• Time in Patent Office: 917 Days
• CPC Class Codes: A61B 8/5207 involving processing of raw data to produce diagnostic data, e.g. for generating an image reconstruction G06T11/00
• CPC Class Codes: A61B 8/54 Control of the diagnostic device
• CPC Class Codes: A61B 8/56 Details of data transmission or power supply
• CPC Class Codes: G01S 7/52033 Gain control of receivers for seismic signals G01V1/245
• CPC Class Codes: H03M 1/0617 characterised by the use of methods or means not specific to a particular type of detrimental influence
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication

Abstract

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.

Claims

1. A time gain compensation (TGC) circuit for an ultrasound device, comprising:

a first amplifier having a first integrating capacitor; and

a control circuit configured to control a gain of the first amplifier by generating a TGC control signal that controls an integration time of the first integrating capacitor, the integration time comprising an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.

2. The TGC circuit of claim 1, wherein the first amplifier comprises a differential amplifier.

3. The TGC circuit of claim 2, wherein the differential amplifier comprises an analog-to-digital converter (ADC) driver.

4. The TGC circuit of claim 1, wherein the control circuit further comprises:

a second amplifier having a feedback capacitor, the second amplifier configured as a comparator circuit, wherein the control circuit generates the TGC control signal by a comparison between an output voltage of the second amplifier and a threshold voltage determined by a value of a variable gain control input signal.

5. The TGC circuit of claim 4, wherein the second amplifier comprises an operational amplifier.

6. The TGC circuit of claim 4, wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.

7. The TGC circuit of claim 6, wherein an output gain of the first amplifier is proportional to a ratio between resistance and capacitance values of the control circuit and resistance and capacitance values of the first amplifier.

8. The TGC circuit of claim 7, wherein the ratio is about 5.

9. The TGC circuit of claim 1, wherein the first integrating capacitor also comprises a sample and hold capacitor of an analog-to-digital converter (ADC).

10. The TGC circuit of claim 9, further comprising an offset voltage capacitor configured to store and cancel an offset voltage associated with the input signal to the first amplifier, and to store and cancel an offset voltage associated with the first amplifier itself.

11. An analog-to-digital converter (ADC) driver circuit for an ultrasound device, comprising:

a first amplifier having first and second integrating capacitors in a feedback configuration; and

a control circuit configured to provide time gain compensation by controlling a gain of the first amplifier by generating a time gain compensation (TGC) control signal that controls an integration time of the first and second integrating capacitors, the integration time comprising an amount of time that an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.

12. The ADC driver circuit of claim 11, wherein the first amplifier comprises a differential amplifier.

13. The ADC driver circuit of claim 12, further comprising a pair of ADC sample and hold capacitors selectively coupled to output terminals of the differential amplifier.

14. The ADC driver circuit of claim 13, further comprising a pair of offset voltage capacitors coupled to input terminals of the differential amplifier.

15. The ADC driver circuit of claim 14, further comprising:

a first pair of switches configured to discharge the first and second integrating capacitors during a reset mode of operation;

a second pair of switches configured to couple the input signal to the differential amplifier following the reset mode of operation, and to thereafter isolate the input signal from the differential amplifier according to the TGC control signal, the second pair of switches also configured to couple the input signal to the offset voltage capacitors during an offset cancellation mode of operation;

a third pair of switches configured to equalize the input and output terminals of the differential amplifier during the offset cancellation mode; and

a fourth pair of switches configured to couple the output terminals of the differential amplifier to the ADC sample and hold capacitors during a sample mode of operation.

16. The ADC driver circuit of claim 11, wherein the control circuit further comprises:

a second amplifier having a feedback capacitor, the second amplifier configured as a comparator circuit; and

wherein the TGC control signal is generated by a comparison between an output voltage of the second amplifier and a threshold voltage determined by a value of a variable gain control input signal.

17. The ADC driver circuit of claim 16, wherein the second amplifier comprises an operational amplifier.

18. The ADC driver circuit of claim 17, wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant and a voltage of the variable gain control input signal.

19. The ADC driver circuit of claim 18, wherein the feedback capacitor of the control circuit is charged with a constant current such that a state of the TGC control signal changes once the output voltage of the operational amplifier exceeds the threshold voltage determined by the variable gain control input signal.

20. The ADC driver circuit of claim 19, further comprising a switch configured to selectively discharge the feedback capacitor.

21. An ultrasound system, comprising:

a receive channel configured to receive electrical signals from an ultrasonic transducer; and

an analog circuit block having an input coupled to the receive channel and an output coupled to an analog-to-digital converter (ADC), the analog circuit block further comprising;

an ADC driver circuit including a differential amplifier having first and second integrating capacitors in a feedback configuration; and

a control circuit configured to provide time gain compensation by generating a time gain compensation (TGC) control signal that controls an integration time of the first and second integrating capacitors, the integration time comprising an amount of time that an input signal is coupled to the differential amplifier before the input signal is isolated from the differential amplifier.

22. The ultrasound system of claim 21, wherein the ADC driver circuit further comprises:

a pair of ADC sample and hold capacitors selectively coupled to output terminals of the differential amplifier;

a pair of offset voltage capacitors coupled to input terminals of the differential amplifier;

a first pair of switches configured to discharge the first and second integrating capacitors during a reset mode of operation;

a second pair of switches configured to couple the input signal to the differential amplifier following the reset mode of operation, and to thereafter isolate the input signal from the differential amplifier according to the TGC control signal, the second pair of switches also configured to couple the input signal to the offset voltage capacitors during an offset cancellation mode of operation;

a third pair of switches configured to equalize the input and output terminals of the differential amplifier during the offset cancellation mode; and

a fourth pair of switches configured to couple the output terminals of the differential amplifier to the ADC sample and hold capacitors during a sample mode of operation.

23. The ultrasound system of claim 22, wherein the control circuit further comprises:

an operational amplifier having a feedback capacitor, the operational amplifier configured as a comparator circuit; and

wherein the TGC control signal is generated by a comparison between an output voltage of the operational amplifier and a threshold voltage determined by a value of a variable gain control input signal.

24. The ultrasound system of claim 23, wherein the integration time controlled by the TGC control signal is dependent upon a capacitance of the feedback capacitor and a voltage of the variable gain control input signal.

25. The ultrasound system of claim 24, wherein the feedback capacitor of the control circuit is charged with a constant current such that a state of the TGC control signal changes once the output voltage of the operational amplifier exceeds the threshold voltage determined by the variable gain control input signal.

26. The ultrasound system of claim 25, wherein the control circuit further comprises a switch configured to selectively discharge the feedback capacitor.

27. The ultrasound system of claim 21, wherein the first and second integrating capacitors also serve as a pair of ADC sample and hold capacitors.

28. The ultrasound system of claim 27, further comprising:

a first pair of switches configured to discharge the first and second integrating capacitors during a reset mode of operation;

a second pair of switches configured to couple the input signal to the differential amplifier following the reset mode of operation, and to thereafter isolate the input signal from the differential amplifier according to the TGC control signal; and

a third pair of switches configured to couple a common mode voltage to input and output terminals of the differential amplifier during the reset mode of operation.

29. The ultrasound system of claim 27, further comprising:

a first pair of switches configured to discharge the first integrating capacitor during a reset mode of operation;

a second pair of switches configured to discharge the second integrating capacitor during the reset mode of operation;

a third pair of switches configured to equalize input and output terminals of the differential amplifier during the reset mode of operation; and

a fourth pair of switches configured to couple the first integrating capacitor to the input and output terminals of the differential amplifier following the reset mode of operation.

30. The ultrasound system of claim 27, wherein the control circuit further comprises:

an operational amplifier having a feedback capacitor, the operational amplifier configured as a comparator circuit; and

wherein the TGC control signal is generated by a comparison between an output voltage of the operational amplifier and a threshold voltage determined by a value of a variable gain control input signal.

31. The ultrasound system of claim 30, wherein the integration time controlled by the TGC control signal is dependent upon an RC time constant of the control circuit and a voltage of the variable gain control input signal.