Continuous application and decompression of test patterns and selective compaction of test responses

• US 10,234,506 B2
• Filed: 05/30/2017
• Issued: 03/19/2019
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Janusz, Tyszer, Jerzy, Kassab, Mark, Mukherjee, Nilanjan
• Primary Examiner(s): Britt, Cynthia
• Application Number:
  US15/608,716
• Publication Number:
  US 20180017622A1
• Time in Patent Office: 658 Days
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Claims

1. A system, comprising:

a circuit comprising a decompressor, the decompressor comprising a linear feedback shift register (LFSR) configured to decompress compressed test pattern bits, wherein the decompressing comprises logically combining the compressed test pattern bits with bits stored within the decompressor, wherein the decompressor further includes a phase shifter having inputs coupled to outputs of the LFSR, the phase shifter being configured such that test pattern bits output from the phase shifter are out of phase with one another; and

automatic testing equipment located external to the circuit.

2. The system of claim 1, wherein the circuit further includes scan chains coupled to the decompressor.

3. A method, comprising:

loading compressed test pattern bits into a decompressor comprising a linear feedback shift register (LFSR); and

decompressing the compressed test pattern bits with the decompressor, wherein the decompressing comprises logically combining the compressed test pattern bits with bits stored within the decompressor, wherein the decompressor further comprises a phase shifter.

4. The method of claim 3, wherein the loading comprises loading the compressed test pattern bits from external automatic testing equipment (ATE).

5. The method of claim 3, further including loading scan chains with the decompressed test pattern bits.