Method for reducing threading dislocation of semiconductor device

• US 10,234,629 B2
• Filed: 05/09/2018
• Issued: 03/19/2019
• Est. Priority Date: 12/20/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Huangfu, Yourui
• Primary Examiner(s): Ullah, Akm E
• Application Number:
  US15/975,496
• Publication Number:
  US 20180259708A1
• Time in Patent Office: 314 Days
• CPC Class Codes: G02B 2006/12123 Diode
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 31/02325 the optical elements not being integrated nor being directly associated with the device
• CPC Class Codes: H01L 31/1035 the devices comprising active layers formed only by AIIIBV compounds
• CPC Class Codes: H01L 33/00 Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K50/00 takes precedence; devices consisting of a plurality of semiconductor components formed in or on a common substrate and including semiconductor components having potential barriers, specially adapted for light emission H01L27/15; semiconductor lasers H01S5/00
• CPC Class Codes: H01S 5/00 Semiconductor lasers superluminescent diodes H01L33/00
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/0218 : Substrates comprising semiconducting materials from other groups of the Periodic Table than the materials of the active layer
• CPC Class Codes: H01S 5/02257 : using windows, e.g. specially adapted for back-reflecting light to a detector inside the housing
• CPC Class Codes: H01S 5/026 : Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/3013 : AIIIBV compounds
• CPC Class Codes: H01S 5/323 : in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

Abstract

A semiconductor device and a method for producing a semiconductor device are disclosed. The semiconductor device includes a first silicon layer; a first dielectric layer, located on the first silicon layer, where the first dielectric layer includes a window, and a bottom horizontal size of the window of the first dielectric layer is not greater than 20 nm; and a III-V semiconductor layer, located on the first dielectric layer and in the window of the first dielectric layer, and connected to the first silicon layer in the window of the first dielectric layer. A III-V semiconductor material of the semiconductor device has no threading dislocations, and therefore has relatively high performance.

Claims

1. A method for producing a semiconductor device, comprising:

etching a silicon layer of silicon on insulator (SOI) using a patterned template as a mask, the SOI comprising a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer, a first window of the silicon layer being etched to expose the dielectric layer, and a bottom horizontal size of the first window being less than a top horizontal size of the first window;

etching the dielectric layer using the silicon layer having the first window as a template, a second window of the dielectric layer being etched to expose the silicon substrate, the second window of the dielectric layer being shaped to limit a size of contact surface exposed over the silicon substrate, and a bottom horizontal size of the second window being less than a top horizontal size of the second windows; and

growing a semiconductor material in the second window of the dielectric layer to form a buffer layer, the semiconductor material being further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the second window of the dielectric layer, the size of the contact surface being based on the bottom horizontal size of the second window of the dielectric layer, and the bottom horizontal size of the second window not being grater than twenty nanometers (nm).

2. The method of claim 1, wherein the semiconductor material is a III-V semiconductor material.

3. The method of claim 1, further comprising sheltering a partial region of the patterned template using a photoresist so that the silicon layer under the sheltered region is not etched.

4. The method of claim 3, further comprising producing a waveguide in the silicon layer that is not etched.

5. A non-transitory computer readable medium, comprising computer program code, which, when executed by a computer unit, will cause the computer unit to:

etch a silicon layer of silicon on insulator (SOI) using a patterned template as a mask, the SOI comprising a silicon substrate, a dielectric layer on the silicon substrate, and the silicon layer on the dielectric layer, a first window of the silicon layer being etched to expose the dielectric layer, and a bottom horizontal size of the first window being less than a top horizontal size of the first window;

etch the dielectric layer using the silicon layer having the first window as a template, a second window of the dielectric layer being etched to expose the silicon substrate, the window of the dielectric layer being shaped to limit a size of contact surface exposed over the silicon substrate, and a bottom horizontal size of the second window being less than a top horizontal size of the second window; and

grow a semiconductor material in the second window of the dielectric layer to form a buffer layer, the semiconductor material being further grown on the buffer layer to obtain a semiconductor layer, the limited size of the contact surface to reduce threading dislocations of the semiconductor material within the second window of the dielectric layer, the size of the contact surface being based on the bottom horizontal size of the second window of the dielectric layer, and the bottom horizontal size of the second window not being greater than twenty nanometers (nm).

6. The computer readable medium of the claim 5, the computer program code further causing the computer unit to shelter a partial region of the patterned template using a photoresist so that the silicon layer under the sheltered region is not etched.

7. The computer readable medium of the claim 6, the computer program code further causing the computer unit to produce a waveguide in the silicon layer that is not etched.