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Method of reducing power dissipation in a clock distribution network for integrated circuit

  • US 10,234,892 B2
  • Filed: 03/02/2018
  • Issued: 03/19/2019
  • Est. Priority Date: 01/10/2017
  • Status: Active Grant
First Claim
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1. A clock distribution network comprising:

  • a transmission line configured to distribute a high-speed clock signal; and

    a multi-port electrical network coupled between first and second segments of the transmission line, the multi-port electrical network comprising series and shunt reactive circuit elements configured to produce first and second resonances that cooperate to create a bandpass response across a plurality of clock distribution frequencies associated with a bandwidth of a combination of the transmission line and the multi-port electrical network.

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