Methods and apparatus for multiple memory maps and multiple page caches in tiered memory

• US 10,235,291 B1
• Filed: 09/20/2016
• Issued: 03/19/2019
• Est. Priority Date: 05/28/2014
• Status: Active Grant

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Michaud, Adrian, Clark, Roy E., Taylor, Kenneth J.
• Primary Examiner(s): Wong, Nanci N
• Application Number:
  US15/270,360
• Time in Patent Office: 910 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/653 Page colouring
• CPC Class Codes: G06F 2212/657 : Virtual address space management
• CPC Class Codes: G06F 2212/7201 : Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 : Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/067 : Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/40607 : Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Methods and apparatus for computer systems having first and second memory tier having regions, physical memory having page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier, and virtual memory having mmaps of ones of the regions in the first memory tier and ones of the regions in the second memory tier, wherein the mmaps are associated with multiple ones of the pages caches.

Claims

1. A method, comprising:

accessing a first memory tier having regions;

accessing a second memory tier having regions;

accessing physical memory having a plurality of page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier; and

utilizing virtual memory having mmaps mapping each of the regions in the first memory tier and the second memory tier to one or more page caches of the plurality of page caches, wherein a first one of the plurality of page caches is shared by a first region in the first memory tier and a first region in the second memory tier,

wherein the virtual memory having mmaps includes a first mmap of the first region in the first memory tier and a second mmap of the first region in the second memory tier, wherein the first and second mmaps are associated with the first one of the plurality of page caches.

2. The method according to claim 1, wherein the page caches are dynamically configurable in size.

3. The method according to claim 1, wherein the first memory tier is provided as storage class memory (SCM), and wherein data moves between the SCM and the page caches on an on-demand page basis.

4. The method according to claim 1, wherein the page caches are sized and managed independently of each other.

5. The method according to claim 1, wherein the page caches are associated with different levels of service with isolation between multiple tenants.

6. The method according to claim 1, wherein the mmaps are created by multiple processes.

7. A computer system, comprising:

a first memory tier having regions;

a second memory tier having regions;

physical memory having a plurality of page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier; and

virtual memory having mmaps mapping each of the regions in the first memory tier and the second memory tier to one or more page caches of the plurality of page caches, wherein a first one of the plurality of page caches is shared by a first region in the first memory tier and a first region in the second memory tier,

wherein the virtual memory having mmaps includes a first mmap of the first region in the first memory tier and a second mmap of the first region in the second memory tier, wherein the first and second mmaps are associated with the first one of the plurality of page caches.

8. The system according to claim 7, wherein the page caches are dynamically configurable in size.

9. The system according to claim 7, wherein the page caches are provided as DRAM.

10. The system according to claim 7, wherein the first memory tier is provided as storage class memory (SCM).

11. The system according to claim 10, wherein data moves between the SCM and the page caches on an on-demand page basis.

12. The system according to claim 7, wherein the page caches are sized and managed independently of each other.

13. The system according to claim 7, wherein the page caches are associated with different levels of service with isolation between multiple tenants.

14. The system according to claim 7, wherein the mmaps are created by multiple processes.

15. An article, comprising:

a non-transitory computer readable medium having stored instructions that enable a machine to;

access a first memory tier having regions;

access a second memory tier having regions;

access physical memory having a plurality of page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier; and

access virtual memory having mmaps mapping each of the regions in the first memory tier and the second memory tier to one or more page caches of the plurality of page caches, wherein a first one of the plurality of page caches is shared by a first region in the first memory tier and a first region in the second memory tier,

wherein the virtual memory having mmaps includes a first mmap of the first region in the first memory tier and a second mmap of the first region in the second memory tier, wherein the first and second mmaps are associated with the first one of the plurality of page caches.

16. The article according to claim 15, wherein the page caches are dynamically configurable in size.

17. The article according to claim 15, wherein the first memory tier is provided as storage class memory (SCM), and wherein data moves between the SCM and the page caches on an on-demand page basis.

18. The article according to claim 15, wherein the page caches are sized and managed independently of each other.

19. The article according to claim 15, wherein the page caches are associated with different levels of service with isolation between multiple tenants.

20. The article according to claim 15, wherein the mmaps are created by multiple processes.