Mechanism for creating friendly transactions with credentials

• US 10,235,297 B2
• Filed: 11/04/2015
• Issued: 03/19/2019
• Est. Priority Date: 11/04/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Busaba, Fadi Y., Gschwind, Michael Karl, Salapura, Valentina, Schwarz, Eric M., Shum, Chung-Lung K.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Cheong, Andrew J
• Application Number:
  US14/932,726
• Publication Number:
  US 20170123992A1
• Time in Patent Office: 1,231 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 16/38 Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.

Claims

1. A system for granting access to a cache line in a transactional memory execution environment, comprising:

a memory;

a processor device; and

a system controller communicatively coupled to the processor device and the memory, wherein the system controller is configured to;

receive a first request from a first transaction to access a cache line;

determine, in response to receiving the first request, that the cache line is used by a second transaction;

determine if the first transaction and the second transaction opt-in to a transaction potential conflict check;

perform, based on an opt-in of the first transaction and the second transaction for the transaction potential conflict check, the transaction potential conflict check between the first transaction and the second transaction in order to compare credentials and determine whether the first transaction and the second transaction are compatible, wherein performing the transaction potential conflict check includes at least determining whether the first transaction and the second transaction have a shared address space within the memory, the memory having one or more memory partitions supporting one or more address spaces, the transaction potential conflict check comprising;

comparing a first token of the first transaction to a second token of the second transaction, and

in response to determining that the first token is the same as the second token, determining that the first transaction and the second transaction are compatible and do not have the shared address space within the memory; and

allow, in response to performing the transaction potential conflict check and determining that the first transaction and the second transaction are compatible and do not have the shared address space within the memory, concurrent access of the cache line for the first transaction and the second transaction such that the first transaction writes to the cache line and the second transaction writes to the cache line concurrently.

2. The system of claim 1, wherein the system controller is further configured to:

obtain a first token type for the first transaction and a second token type for the second transaction based on an opt-in of the first transaction and the second transaction for the transaction potential conflict check.

3. The system of claim 2, wherein obtaining the first token type and the second token type, causes the system controller to:

receive the first token type from a token manager and augment a transaction handling protocol with a token type assigned to the first transaction;

complete the first transaction; and

return the first token type to the token manager.

4. The system of claim 2, wherein the first transaction and the second transaction are determined to be compatible in response to the second token type of the second transaction being identical to the first token type of the first transaction.

5. The system according to claim 1, wherein the system controller is further configured to:

suppress detection of cache coherent conflicts for the cache line in response to allowing concurrent access to the cache line.

6. A computer program product for granting access to a cache line in a transactional memory execution environment comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable storage medium does not comprise a transitory signal per se, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive a first request from a first transaction to access a cache line;

determine, in response to receiving the first request, that the cache line is used by a second transaction;

determine if the first transaction and the second transaction opt-in to a transaction potential conflict check;

perform, based on an opt-in of the first transaction and the second transaction for the transaction potential conflict check, the transaction potential conflict check between the first transaction and the second transaction in order to compare credentials and determine whether the first transaction and the second transaction are compatible, wherein performing the transaction potential conflict check includes at least determining whether the first transaction and the second transaction have a shared address space within the memory, the memory having one or more memory partitions supporting one or more address spaces, the transaction potential conflict check comprising;

comparing a first token of the first transaction to a second token of the second transaction, and

in response to determining that the first token is the same as the second token, determining that the first transaction and the second transaction are compatible and do not have the shared address space within the memory; and

allow, in response to performing the transaction potential conflict check and determining that the first transaction and the second transaction are compatible and do not have the shared address space within the memory, concurrent access of the cache line for the first transaction and the second transaction such that the first transaction writes to the cache line and the second transaction writes to the cache line concurrently.

7. The computer program product of claim 6, wherein the computer readable program causes the computing device to:

obtain a first token type for the first transaction and a second token type for the second transaction based on the opt-in of the first transaction and the second transaction for the transaction potential conflict check.

8. The computer program product of claim 7, wherein obtaining the first token type and the second token type causes the computing device to:

receive the first token type from a token manager and augment a transaction handling protocol with a token type assigned to the first transaction;

complete the first transaction; and

return the first token type to the token manager.

9. The computer program product of claim 7, wherein the first transaction and the second transaction are determined to be compatible in response to the second token type of the second transaction being identical to the first token type of the first transaction.

10. The computer program product according to claim 6, wherein the computer readable program further causes the computing device to:

suppress detection of cache coherent conflicts for the cache line in response to allowing concurrent access to the cache line.