Methods and systems for centering of pins during instance abutment

• US 10,235,490 B1
• Filed: 05/08/2017
• Issued: 03/19/2019
• Est. Priority Date: 05/08/2017
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Mallon, David, Lamant, Gilles S. C., Ferguson, Kenneth, Bijoy, Monika
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US15/589,731
• Time in Patent Office: 680 Days
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G16H 10/60 for patient-specific data, e.g. for electronic patient records
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass

Abstract

Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Claims

1. A computer implemented method for abutting circuit devices in an integrated circuit design, the method comprising:

receiving, by a computer, a plurality of database records of a plurality of circuit devices forming an integrated circuit (IC), wherein a first circuit device of the plurality of circuit devices includes a first set of pin figures and a second circuit device of the plurality of circuit devices includes a second set of pin figures;

determining, by the computer, that a first pin figure of the first set of pin figures is to be overlapped with a second pin figure of the second set of pin figures based upon the location data of the first circuit device and the second circuit device in the respective database records;

identifying, by the computer, a first center location of the first pin figure and a second center location of the second pin figure based on the location data of the first circuit device and the second circuit device in the respective database records;

positioning, by the computer, at least one of the first circuit and second circuit devices such that the first center location and the second center location overlap;

generating, by the computer, a third circuit device formed by abutting first and second circuit devices and having a portion formed by merging and optimizing the overlapping first and second pin figures; and

updating, by the computer, the respective database records of the first and second circuit devices based on the generating of the third circuit device formed by abutting first and second circuit devices, whereby the computer provides a computationally efficient and a flexible centering of the first and second pin figures.

2. The method of claim 1, wherein at least one of the first and second circuit devices is represented by a pcell instance.

3. The method of claim 1, wherein at least one of the first and second circuit devices is represented by a first fixed cell instance.

4. The method of claim 1, wherein at least one of the first and second circuit devices is a transistor.

5. The method of claim 1, wherein at least one of the first and second circuit devices is an optical waveguide or a radio frequency (RF) transmission line.

6. The method of claim 1, further comprising:

determining, by the computer, that the first pin figure of the first set of pin figures is to be overlapped with the second pin figure of the second set of pin figures based upon rectilinear access directions of the first and second pin figures.

7. The method of claim 1, further comprising:

automatically identifying, by the computer system, that the first and second circuit devices from the plurality of circuit devices are to be abutted based on the proximity of the first and second devices determined based on location data of the first and second circuit devices in the respective database records.

8. The method of claim 1, further comprising:

receiving, by the computer, an indication from a user that the first and second circuit devices of the plurality of circuit devices are to be abutted.

9. The method of claim 1, wherein the first circuit device is a first optical waveguide and the second device is a second optical waveguide, and wherein the abutting of the first and second optical waveguide forms a combined and continuous optical waveguide.

10. The method of claim 1, further comprising:

rendering, by the computer, the first and second circuit devices including the respective set of pin figures on a graphical user interface (GUI); and

updating, by the computer, the GUI based on abutting the first and second circuit devices.

11. A system for abutting circuit devices in an integrated circuit design, the system comprising:

one or more computers comprising a non-transitory machine-readable media configured to store a plurality of database records of a plurality of circuit devices, wherein a first circuit device of the plurality of circuit devices includes a first set of pin figures and a second circuit device of the plurality of circuit devices includes a second set of pin figures;

at least one computer of the one or more computers, the at least one computer coupled to the non-transitory machine readable media storing the plurality of database records and comprising a processor configured to;

determine that a first pin figure of the first set of pin figures is to be overlapped with a second pin figure of the second set of pin figures based upon the location data of the first circuit device and the second circuit device in the respective database records;

identify a first center location of the first pin figure and a second center location of the second pin figure based on the location data of the first circuit device and the second circuit device in the respective database records;

position at least one of the first circuit and second circuit devices such that the first center location and the second center location overlap;

generate a third circuit device formed by abutting first and second circuit devices and having a portion formed by merging and optimizing the overlapping first and second pin figures; and

update the respective database records of the first and second circuit devices based on the generating of the third circuit device formed by abutting first and second circuit devices, whereby the at least one computer provides a computationally efficient and a flexible centering of the first and second pin figures.

12. The system of claim 11, wherein at least one of the first and second circuit devices is represented by a pcell instance.

13. The system of claim 11, wherein at least one of the first and second circuit devices is represented by a first fixed cell instance.

14. The system of claim 11, wherein at least one of the first and second circuit devices is a transistor.

15. The system of claim 11, wherein at least one of the first and second circuit devices is an optical waveguide or a radio frequency (RF) transmission line.

16. The system of claim 11, wherein the processor is further configured to:

determine that the first pin figure of the first set of pin figures is to be overlapped with the second pin figure of the second set of pin figures based upon rectilinear access directions of the first and second pin figures.

17. The system of claim 11, wherein the processor is further configured to:

automatically identify that the first and second circuit devices from the plurality of circuit devices are to be abutted based on the proximity of the first and second devices determined based on location data of the first and second circuit devices in the respective database records.

18. The system of claim 11, wherein the processor is further configured to:

receive an indication from a user that the first and second circuit devices of the plurality of circuit devices are to be abutted.

19. The system of claim 11, wherein the first circuit device is a first optical waveguide and the second device is a second optical waveguide, and wherein the abutting of the first and second optical waveguide forms a combined and continuous optical waveguide.

20. The system of claim 11, wherein the processor is further configured to:

render the first and second circuit devices including the respective set of pin figures on a graphical user interface (GUI); and

update the GUI based on abutting the first and second circuit devices.