Dynamic route keep-out in printed circuit board design

• US 10,235,491 B2
• Filed: 05/17/2017
• Issued: 03/19/2019
• Est. Priority Date: 05/17/2017
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Christo, Michael A., Green, David L., Maldonado, Julio A., Zurovetz, Diana D.
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US15/597,496
• Publication Number:
  US 20180336306A1
• Time in Patent Office: 671 Days
• Field of Search: 716126, 716137, 716104, 716106, 716108, 716116, 716128, 716131
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Dynamic electronic printed circuit board (PCB) design is provided. A voltage split having a first geometric shape in a first layer of the PCB is identified. Based on the voltage split, a boundary having a second geometric shape is created in an adjacently positioned layer of the PCB with respect to the first layer. A net having at least two pins is dynamically routed in the PCB. An intersection of the net with the first boundary is identified and dynamically resolved.

Claims

1. A computer system for dynamic electronic printed circuit board (PCB) design comprising:

a processor in communication with a memory;

a design module in communication with the processor and memory, the memory comprising instructions to cause the design module to;

identify a voltage split having a first geometric shape in a first layer of a PCB;

dynamically create a first boundary in one or more adjacently positioned layers of the PCB with respect to the first layer, the first boundary having a second geometric shape corresponding to the first geometric shape;

dynamically route a net having at least two pins in the PCB including determine a first route for one or more wires to connect the at least two pins;

identifying a route exception including determine the first route intersects the first boundary in at least one of the adjacently positioned layers; and

dynamically resolve the route exception; and

a PCB model file generated by the design module, and manufacture the PCB from the generated file.

2. The system of claim 1, further comprising the design module to:

determine one or more parameters of the net, the parameters selected from the group consisting of;

a wire spacing, importance factor, maximum distance of a wire, a minimum distance of a wire, a quantity of VIAs, and a distance from a boundary, wherein the determination of the first route including the wires, conforms to the net parameters.

3. The system of claim 1, wherein the dynamic resolution further comprises the design module to:

determine a second route for the wires that avoids the first boundary;

select the second route as a viable route for the wires; and

route the net according to the selected viable route.

4. The system of claim 3, wherein the second route determination further comprises the design module to:

create a vertical interconnect access (VIA) to a second layer of the PCB; and

determine a route segment in the second layer that bypasses the first boundary, wherein the second route includes the VIA and the route segment.

5. The system of claim 1, wherein the dynamic resolution further comprises the design module to:

create a break in at least one of the wires based on a location of the intersection.

6. The system of claim 1, wherein the voltage split is a region between two different voltage shapes in the first layer of the PCB.

7. The system of claim 1, wherein the dynamic resolution further comprises the design module to:

change the first geometric shape of the voltage split to a third geometric shape;

create a second boundary in the adjacently positioned layers of the PCB, the second boundary having a fourth geometric shape corresponding to the third geometric shape; and

determine the first route avoids the second boundary;

select the first route as a viable route for the wires; and

route the net according to the selected viable route.

8. A computer program product for dynamic electronic printed circuit board (PCB) design, the computer program product comprising a computer readable storage device having program code embodied therewith, the program code executable by a processor to generate a PCB model file, including:

identify a voltage split having a first geometric shape in a first layer of a PCB;

dynamically create a first boundary in one or more adjacently positioned layers of the PCB with respect to the first layer, the first boundary having a second geometric shape corresponding to the first geometric shape;

dynamically route a net having at least two pins in the PCB including determine a first route for one or more wires to connect the at least two pins;

identify a route exception including determine the first route intersects the first boundary in at least one of the adjacently positioned layers; and

dynamically resolve the route exception; and

utilizing the file to manufacture the PCB.

9. The computer program product of claim 8, further comprising program code to:

determine one or more parameters of the net, the parameters selected from the group consisting of;

wire spacing, importance factor, maximum distance of a wire, a minimum distance of a wire, a quantity of VIAs, and a distance from a boundary, wherein the determination of the first route including the wires, conforms to the net parameters.

10. The computer program product of claim 8, wherein the dynamic resolution further comprises program code to:

determine a second route for the wires that avoids the first boundary;

select the second route as a viable route for the wires; and

route the net according to the selected viable route.

11. The computer program product of claim 10, wherein the second route determination further comprises program code to:

create a vertical interconnect access (VIA) to a second layer of the PCB; and

determine a route segment in the second layer that bypasses the first boundary, wherein the second route includes the VIA and the route segment.

12. The computer program product of claim 8, wherein the voltage split is a region between two different voltage shapes in the first layer of the PCB.

13. The computer program product of claim 8, wherein the dynamic resolution further comprises program code to:

change the first geometric shape of the voltage split to a third geometric shape;

create a second boundary in the adjacently positioned layers of the PCB, the second boundary having a fourth geometric shape corresponding to the third geometric shape; and

determine the first route avoids the second boundary;

select the first route as a viable route for the wires; and

route the net according to the selected viable route.

14. A method for dynamic electronic printed circuit board (PCB) design comprising:

generating a PCB model file including;

identifying a voltage split having a first geometric shape in a first layer of a PCB;

dynamically creating a first boundary in one or more adjacently positioned layers of the PCB with respect to the first layer, the first boundary having a second geometric shape corresponding to the first geometric shape;

dynamically routing a net having at least two pins in the PCB including, determining a first route for one or more wires to connect the at least two pins;

identifying a route exception including determining the first route intersects the first boundary in at least one of the adjacently positioned layers; and

dynamically resolving the route exception; and

utilizing the file to manufacture the PCB.

15. The method of claim 14, further comprising:

determining one or more parameters of the net, the parameters selected from the group consisting of;

wire spacing, importance factor, maximum distance of a wire, a minimum distance of a wire, a quantity of VIAs, and a distance from a boundary, wherein the determination of the first route including the wires, conforms to the net parameters.

16. The method of claim 14, wherein dynamically resolving the route exception further comprises:

determining a second route for the wires that avoids the first boundary;

selecting the second route as a viable route for the wires; and

routing the net according to the selected viable route.

17. The method of claim 16, wherein determining a second route for the one or more wires that avoids the first boundary further comprises:

creating a vertical interconnect access (VIA) to a second layer of the PCB; and

determining a route segment in the second layer that bypasses the first boundary, wherein the second route includes the VIA and the route segment.

18. The method of claim 14, wherein dynamically resolving the route exception further comprises:

creating a break in at least one of the wires based on a location of the intersection.

19. The method of claim 14, wherein the voltage split is a region between two different voltage shapes in the first layer of the PCB.

20. The method of claim 14, wherein dynamically resolving the route exception further comprises:

changing the first geometric shape of the voltage split to a third geometric shape;

creating a second boundary in the adjacently positioned layers of the PCB, the second boundary having a fourth geometric shape corresponding to the third geometric shape; and

determining the first route avoids the second boundary;

selecting the first route as a viable route for the wires; and

routing the net according to the selected viable route.