Techniques for robust reliability operation of a thin-film transistor (TFT) display

• US 10,235,962 B2
• Filed: 12/23/2016
• Issued: 03/19/2019
• Est. Priority Date: 12/23/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Choi, Minhyuk, Zheng, Ying, Morris, Matthew, Cady, Andrew, Hill, Jerry Michael, Lee, Gangok, Dighde, Rajesh
• Primary Examiner(s): Sherman, Stephen G
• Application Number:
  US15/389,831
• Publication Number:
  US 20180182349A1
• Time in Patent Office: 816 Days
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2320/048 using evaluation of the usage time
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/028 Generation of voltages supplied to electrode drivers in a matrix display other than LCD
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

The present disclosure provides devices and techniques for dynamically adjusting the bias voltage (V) levels (e.g., low level gate voltage (VGL) and high level gate voltage (VGH)) for display screens made with thin-film transistor (TFT) technology based on a display run time. Thus, as the positive bias temperature stress for the TFTs increases over the course of the display lifetime, features of the present disclosure adjust the bias voltage levels to maintain operation margin (e.g., the ratio between the high level gate voltage (VGH) value and the voltage value which the display can maintain with normal operation). By dynamically adjusting the bias voltage levels, the TFT displays of the present disclosure consume lower power than their conventional counterparts and improve the lifetime of the display itself.

Claims

1. A method for controlling voltage bias of a thin-film transistor (TFT) display, comprising:

setting a voltage level for the TFT display during a first time period to a first voltage value;

determining a display run time of the TFT display during a second time period; and

dynamically adjusting the voltage level from the first voltage value to a second voltage value based on the display run time and a measured temperature of the TFT display.

2. The method of claim 1, wherein dynamically adjusting the voltage level from the first voltage value to the second voltage value, comprises:

identifying the second voltage value by correlating the display run time of the TFT display with one of the voltage values in a lookup table stored in a memory.

3. The method of claim 1, wherein dynamically adjusting the voltage level from the first voltage value to the second voltage value, comprises:

determining an operation margin between a reference voltage (V_clamp) and a high level gate voltage (VGH) value; and

maintaining the operation margin from the first time period to the second time period by adjusting the voltage level.

4. The method of claim 1, wherein dynamically adjusting the voltage level from the first voltage value to the second voltage value comprises:

adjusting the voltage level in response to an increase of a positive bias temperature stress for the TFT display over the course of the TFT display lifetime.

5. The method of claim 1, wherein the voltage level includes one or more of a low level gate voltage (VGL) value and a high level gate voltage (VGH) value of the TFT display.

6. The method of claim 1, wherein the first voltage value is lower than the second voltage value.

7. The method of claim 1, wherein the TFT display includes at least one TFT with an oxide active layer or a poly-silicon active layer.

8. The method of claim 1, wherein the voltage bias of the TFT display is controlled by a timing controller (TCON) implemented in the TFT display.

9. An apparatus for controlling the voltage bias of a thin-film transistor (TFT) display, comprising:

a processor;

a memory coupled to the processor, wherein the memory includes instructions executable by the processor to;

set a voltage level for the TFT display during a first time period to a first voltage value;

determine a display run time of the TFT display during a second time period; and

dynamically adjust the voltage level from the first voltage value to a second voltage value based on the display run time and a measured temperature of the TFT display.

10. The apparatus of claim 9, wherein the instructions to dynamically adjust the voltage level from the first voltage value to the second voltage value are further executable by the processor to:

identify the second voltage value by correlating the display run time of the TFT display with one of the voltage values in a lookup table stored in the memory.

11. The apparatus of claim 9, wherein the instructions to dynamically adjust the voltage level from the first voltage value to the second voltage value are further executable by the processor to:

determine an operation margin between a reference voltage (V_clamp) and a high level gate voltage (VGH) value; and

maintain the operation margin from the first time period to the second time period by adjusting the voltage level.

12. The apparatus of claim 9, wherein the instructions to dynamically adjust the voltage level from the first voltage value to the second voltage value are further executable by the processor to:

adjust the voltage level in response to an increase of a positive bias temperature stress for the TFT display over the course of the TFT display lifetime.

13. The apparatus of claim 9, wherein the voltage level includes one or more of a low level gate voltage (VGL) value and a high level gate voltage (VGH) value of the TFT display.

14. The apparatus of claim 9, wherein the first voltage value is lower than the second voltage value.

15. A non-transitory computer-readable medium for controlling voltage bias of a thin-film transistor (TFT) display comprising instructions for:

setting a voltage level for the TFT display during a first time period to a first voltage value;

determining a display run time of the display during a second time period; and

dynamically adjusting the voltage level from the first voltage value to a second voltage value based on the display run time and a measured temperature of the TFT display.

16. The non-transitory computer-readable medium of claim 15, wherein instructions for dynamically adjusting the voltage level from the first voltage value to the second voltage value, comprise instructions for:

identifying the second voltage value by correlating the display run time of the TFT display with the voltage level in a lookup table stored in a memory of the TFT display.

17. The non-transitory computer-readable medium of claim 15, wherein instructions for dynamically adjusting the voltage level from the first voltage value to the second voltage value, comprise instructions for:

determining an operation margin between a reference voltage (V_clamp) and a high level gate voltage (VGH) value; and

maintaining the operation margin from the first time period to the second time period by adjusting the voltage level.

18. The non-transitory computer-readable medium of claim 15, wherein instructions for dynamically adjusting the voltage level from the first voltage value to the second voltage value comprise instructions for:

adjusting the voltage level in response to an increase of a positive bias temperature stress for the TFT display over the course of the TFT display lifetime.

19. The non-transitory computer-readable medium of claim 15, wherein the voltage level includes one or more of a low level gate voltage (VGL) value and a high level gate voltage (VGH) value of the TFT display.