Emulated multiport memory element circuitry with exclusive-OR based control circuitry

• US 10,236,043 B2
• Filed: 06/06/2016
• Issued: 03/19/2019
• Est. Priority Date: 06/06/2016
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chu, Pohrong Rita
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/174,460
• Publication Number:
  US 20170352393A1
• Time in Patent Office: 1,016 Days
• Field of Search: 36523003, 36523002, 36518902, 365 63, 36523005, 36523004, 711154, 711127
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

Claims

1. Memory element circuitry having a plurality of write ports and a plurality of read ports, the memory element circuitry comprising:

a plurality of banks of dual-port memory elements, wherein each bank in the plurality of banks is coupled to a respective one of the write ports;

a switching circuit coupled between the plurality of banks of dual-port memory elements and a first read port of the plurality of read ports; and

a logic exclusive-OR (XOR) gate coupled to a control input of the switching circuit, wherein the logic XOR gate receives signals based on previously-stored write address signals and outputs a read control signal that controls the switching circuit to selectively route read data from the plurality of banks of dual-port memory elements to the first read port.

2. The memory element circuitry defined in claim 1, wherein the switching circuit has a plurality of inputs and each input of the plurality of inputs is coupled to a different respective bank in the plurality of banks of dual-port memory elements.

3. The memory element circuitry defined in claim 2, wherein the switching circuit has a first input coupled to a read port of a first dual-port memory element in a first bank of the plurality of banks, and wherein the switching circuit has a second input coupled to a read port of a second dual-port memory element in a second bank of the plurality of banks.

4. The memory element circuitry defined in claim 1, wherein each write port of the plurality of write ports conveys write data to each dual-port memory element in a different respective bank of the plurality of banks of dual-port memory elements.

5. The memory element circuitry defined in claim 4, further comprising:

control circuitry that receives a write addressing control signal associated with the write data, wherein the logic XOR gate generates the read control signal based at least partially on the write addressing control signal received by the control circuitry.

6. The memory element circuitry defined in claim 5, wherein the control circuitry comprises:

an additional logic XOR gate that has an input that receives the write addressing control signal; and

a group of dual-port memory elements coupled between an input of the logic XOR gate and an output of the additional logic XOR gate.

7. The memory element circuitry defined in claim 6, wherein the group of dual-port memory elements comprises block Random Access Memory (RAM) circuits each having a single read port and a single write port.

8. The memory element circuitry defined in claim 1, further comprising:

an additional switching circuit coupled between the plurality of banks of dual-port memory elements and a second read port of the plurality of read ports; and

an additional logic XOR gate coupled to a control input of the additional switching circuit, wherein the additional logic XOR gate outputs an additional read control signal that controls the additional switching circuit to selectively route additional read data from the plurality of banks of dual-port memory elements to the second read port.

9. The memory element circuitry defined in claim 8, wherein the switching circuit comprises a first multiplexer having a first input coupled to a read port of a first dual-port memory element in a first bank of the plurality of banks and having a second input coupled to a read port of a second dual-port memory element in a second bank of the plurality of banks, and wherein the additional switching circuit comprises a second multiplexer having a third input coupled to a read port of a third dual-port memory element in the first bank and having a fourth input coupled to a read port of a fourth dual-port memory element in the second bank.

10. The memory element circuitry defined in claim 1, wherein the dual-port memory elements comprise block Random Access Memory (RAM) circuits each having a single write port and a single read port.

11. Memory circuitry that receives write data over a plurality of write ports and that has a plurality of read ports, comprising:

a first set of logic exclusive-OR (XOR) gates that receives addressing control signals associated with the write data;

a second set of logic XOR gates that is different from the first set of logic XOR gates and that generates read control signals based on previously-stored addressing control signals associated with the write data;

a group of dual-port memory elements coupled between the first and second sets of logic XOR gates;

data storage circuitry that stores the write data, wherein the data storage circuitry comprises multiple memory banks; and

switching circuitry coupled between the multiple memory banks, wherein the switching circuitry selectively routes a most recently-written write data value from a particular memory bank of the multiple memory banks in the data storage circuitry to a given read port of the plurality of read ports based on the read control signals generated by the second set of logic XOR gates.

12. The memory circuitry defined in claim 11, wherein the first set of logic XOR gates generates modified addressing control signals based on the received addressing control signals and wherein the group of dual-port memory elements stores the modified addressing control signals.

13. The memory circuitry defined in claim 12, wherein the modified addressing control signals stored on the group of dual-port memory elements are read and provided to inputs of the second set of logic XOR gates and the second set of logic XOR gates generates the read control signals based on the modified addressing signals read from the group of dual-port memory elements.

14. The memory circuitry defined in claim 11, wherein the group of dual-port memory elements comprises a first set of dual-port memory elements having write ports coupled to outputs of the first set of logic XOR gates and having read ports coupled to inputs of the second set of logic XOR gates.

15. The memory circuitry defined in claim 14, wherein the group of dual-port memory elements further comprises a second set of dual-port memory elements having write ports coupled to the outputs of the first set of logic XOR gates and having read ports coupled to inputs of the first set of logic XOR gates.

16. The memory circuitry defined in claim 11, wherein the group of dual-port memory elements comprises:

a first row of dual-port memory elements having write ports that are coupled to an output of a first logic XOR gate in the first set of logic XOR gates; and

a second row of dual-port memory elements having write ports that are coupled to an output of a second logic XOR gate in the first set of logic XOR gates, wherein the first logic XOR gate has a first input that receives a first addressing control signal and a second input that is coupled to an output of a dual-port memory element in the second row, and wherein the second logic XOR gate has a third input that receives a second addressing control signal and a fourth input that is coupled to an output of a dual-port memory element in the first row.

17. The memory circuitry defined in claim 11, wherein the data storage circuitry comprises a plurality of banks of dual-port memory elements, each bank receives a respective write data value, each dual-port memory element in each bank stores a copy of the respective write data value received by that bank, and the switching circuitry selectively routes the most recently-written write data value from a given one of the banks of dual-port memory elements to the given read port based on the read control signals.

18. A method of operating memory circuitry on an integrated circuit, the method comprising:

with a first set of dual-port memory elements, storing write data received over a plurality of write ports of the memory circuitry;

with control circuitry, receiving write addressing signals associated with the write data, processing the write addressing signals, and storing the previously processed write addressing signals on a second set of dual-port memory elements that is different from the first set of dual-port memory elements; and

with exclusive-OR (XOR) logic circuitry, controlling switching circuitry interposed between the first set of dual-port memory elements and a plurality of read ports of the memory circuitry to selectively route the write data stored on selected dual-port memory elements of the first set of dual-port memory elements to a plurality of read ports of the memory circuitry based on the previously processed write addressing signals stored on the second set of dual-port memory elements.

19. The method defined in claim 18, wherein the switching circuitry comprises a respective switch coupled to each of the read ports in the plurality of read ports, and wherein the XOR logic circuitry comprises respective XOR logic gates that each provides a respective read control signal to a corresponding one of the respective switches.

20. The method defined in claim 18, further comprising:

at the first set of dual-port memory elements, concurrently receiving the write data over each of the plurality of write ports, wherein controlling the switching circuitry comprises controlling the switching circuitry to concurrently route the write data stored on the first set of dual-port memory elements to each of the plurality of read ports.