Optimizing data approximation analysis using low power circuitry

• US 10,236,050 B2
• Filed: 06/06/2018
• Issued: 03/19/2019
• Est. Priority Date: 06/02/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Erickson, Karl R., Paone, Phil C., Paulik, George F., Paulsen, David P., Sheets, II, John E., Uhlmann, Gregory J.
• Primary Examiner(s): Hoang, Tri M
• Application Number:
  US16/001,420
• Publication Number:
  US 20180350423A1
• Time in Patent Office: 286 Days
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Claims

1. An apparatus for optimizing data approximation analysis using low power circuitry, the apparatus comprising a circuit configured to carry out the steps of:

applying a voltage from a first capacitor and a voltage from a second capacitor to a transistor on the circuit, wherein the first capacitor is charged with a unit of charge for each of a first set of data results that indicates a positive data point, wherein the second capacitor is charged with the unit of charge for each of a second set of data results that indicates a positive data point, and wherein a current flows through the transistor toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltages of the first capacitor and the second capacitor is greater than a threshold voltage of the transistor; and

generating a signal on the output of the circuit to indicate that the positive data points in the first set of data results is greater than the positive data points in the second set of data results and that a difference between the positive data points in the first set of data results and the positive data points in the second set of data results is greater than a probability range.

2. The apparatus of claim 1, the circuit further configured to carry out the steps of:

determining that the charge on the first capacitor has exceeded a capacitor threshold; and

resetting the charges on the first capacitor and the second capacitor to a baseline charge.

3. The apparatus of claim 1, wherein the probability range is calculated as a function of the threshold voltage of the transistor.

4. The apparatus of claim 1, wherein the unit of charge is placed on the first capacitor using a non-inverting level shifter.

5. The apparatus of claim 1, wherein the current flowing through the transistor causes the output of the circuit to indicate a positive result.

6. The apparatus of claim 1, wherein the first capacitor and the second capacitor are charged to a baseline voltage before being charged with the unit of charge.

7. The apparatus of claim 1, wherein the positive data points in the first set of data results indicate a first type of relationship between a first test and a second test, and wherein the positive data points in the second set of data results indicate a second type of relationship between the first test and the second test.

8. A computer program product for optimizing data approximation analysis using low power circuitry, the computer program product disposed upon a non-transitory, computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

applying a voltage from a first capacitor and a voltage from a second capacitor to a transistor on the circuit, wherein the first capacitor is charged with a unit of charge for each of a first set of data results that indicates a positive data point, wherein the second capacitor is charged with the unit of charge for each of a second set of data results that indicates a positive data point, and wherein a current flows through the transistor toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltages of the first capacitor and the second capacitor is greater than a threshold voltage of the transistor; and

generating a signal on the output of the circuit to indicate that the positive data points in the first set of data results is greater than the positive data points in the second set of data results and that a difference between the positive data points in the first set of data results and the positive data points in the second set of data results is greater than a probability range.

9. The computer program product of claim 8, wherein the computer program instructions, when executed, further cause the computer to carry out the steps of:

determining that the charge on the first capacitor has exceeded a capacitor threshold; and

resetting the charges on the first capacitor and the second capacitor to a baseline charge.

10. The computer program product of claim 8, wherein the probability range is calculated as a function of the threshold voltage of the transistor.

11. The computer program product of claim 8, wherein the unit of charge is placed on the first capacitor using a non-inverting level shifter.

12. The computer program product of claim 8, wherein the current flowing through the transistor causes the output of the circuit to indicate a positive result.

13. The computer program product of claim 8, wherein the first capacitor and the second capacitor are charged to a baseline voltage before being charged with the unit of charge.