Memory controller

• US 10,236,051 B2
• Filed: 08/01/2017
• Issued: 03/19/2019
• Est. Priority Date: 04/24/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US15/666,496
• Publication Number:
  US 20180012644A1
• Time in Patent Office: 595 Days
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Claims

1. A memory controller component comprising:

a signaling interface, including;

first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and

second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and

adjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.

2. The memory controller of claim 1 wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.

3. The memory controller of claim 1 wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times, from the memory controller component to the DRAM, of the first and second timing signals.

4. The memory controller of claim 1 wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.

5. The memory controller of claim 4 wherein the circuitry to output at least part of the first write data onto the external data signaling link comprises circuitry to output a sequence of signal levels during respective time intervals defined by transitions of the second timing signal, each signal level of the sequence of signal levels corresponding to a respective bit of the first write data.

6. The memory controller of claim 1 wherein the first timing signal defines a first timing domain within the DRAM and wherein the adjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM comprises circuitry to adjust a phase of the second timing signal such that the second timing signal arrives at the DRAM in phase alignment within the first timing domain.

7. The memory controller of claim 1 wherein the adjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate skew between their arrival times at the DRAM comprises circuitry to offset the first and second timing signals from one another at the signaling interface to effect a predetermined phase relation between the first and second timing signals at the DRAM.

8. The memory controller of claim 7 wherein the predetermined phase relation between the first and second timing signals at the DRAM comprises either (i) edge alignment between the first and second timing signals or (ii) alignment of an edge of the second timing signal with a midpoint between successive edges of the first timing signal.

9. The memory controller of claim 1 wherein the DRAM constitutes a first one of a plurality of DRAMs that are to (i) receive the write command via one or more shared command signaling links and (ii) receive the first timing signal via a shared clock signaling link, the first timing signal arriving at a second DRAM of the plurality of DRAMs at a different time than at the first one of the plurality of DRAMs.

10. The memory controller of claim 9 further comprising third circuitry to transmit second write data to the second DRAM to be sampled therein in response to a third timing signal, and wherein the adjustment circuitry comprises circuitry to offset the first and third timing signals from one another at the signaling interface to compensate for skew between their arrival times at the second DRAM.

11. A method of operation within a memory controller component, the method comprising:

transmitting a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal;

transmitting first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and

offsetting the first and second timing signals from one another at a signaling interface of the memory controller component to compensate for skew between their arrival times at the DRAM.

12. The method of claim 11 wherein offsetting the first and second timing signals from one another comprises offsetting a phase of the second timing signal from a phase of the first timing signal.

13. The method of claim 11 wherein offsetting the first and second timing signals from one another comprises offsetting the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times, from the memory controller component to the DRAM, of the first and second timing signals.

14. The method of claim 11 wherein transmitting the first write data to the DRAM comprises outputting at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.

15. The method of claim 14 wherein outputting at least part of the first write data onto the external data signaling link comprises outputting a sequence of signal levels during respective time intervals defined by transitions of the second timing signal, each signal level of the sequence of signal levels corresponding to a respective bit of the first write data.

16. The method of claim 11 wherein the first timing signal defines a first timing domain within the DRAM and wherein offsetting the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM comprises adjusting a phase of the second timing signal such that the second timing signal arrives at the DRAM in phase alignment within the first timing domain.

17. The method of claim 16 wherein offsetting the first and second timing signals from one another at the signaling interface to compensate skew between their arrival times at the DRAM comprises offsetting the first and second timing signals from one another at the signaling interface to effect a predetermined phase relation between the first and second timing signals at the DRAM.

18. The method of claim 17 wherein the predetermined phase relation between the first and second timing signals at the DRAM comprises either (i) edge alignment between the first and second timing signals or (ii) alignment of an edge of the second timing signal with a midpoint between successive edges of the first timing signal.

19. The method of claim 11 wherein the DRAM comprises a first one of a plurality of DRAMs coupled to (i) receive the write command via one or more shared command signaling links and (ii) to receive the first timing signal via a shared clock signaling link, the first timing signal arriving at a second DRAM of the plurality of DRAMs at a different time than at the first one of the plurality of DRAMs, and wherein the method further comprises:

transmitting second write data to the second DRAM to be sampled therein in response to a third timing signal; and

offsetting the first and third timing signals from one another at the signaling interface to compensate for skew between their arrival times at the second DRAM.

20. A memory controller component comprising:

a signaling interface, including

means for transmitting a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and

means for transmitting first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and

means for offsetting the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.