Current sense amplifiers, memory devices and methods

• US 10,236,052 B2
• Filed: 05/11/2017
• Issued: 03/19/2019
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Na, Onegyun, Kwak, Jongtae, Lee, Seong-Hoon, Choi, Hoon
• Primary Examiner(s): Le, Toan K
• Application Number:
  US15/592,436
• Publication Number:
  US 20170249985A1
• Time in Patent Office: 677 Days
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Claims

1. An amplifier, comprising:

a first transistor coupled between first and second nodes;

a second transistor coupled between third and fourth nodes, a control gate of the first transistor being coupled to the third node and a control gate of the second transistor being coupled to the first node;

a third transistor coupled between the first and third nodes and configured to form a current path between the first and third nodes responsive to a first signal;

a first enable circuit coupled between a first power source node and the first node and between the first power source node and the third node, the first enable circuit configured to form a current path between the first power source node and the first node and between the first power source node and the third node responsive to a second signal different from the first signal; and

a second enable circuit coupled between a second power source node and the second node and between the second power source node and the fourth node, the second enable circuit configured to form a current path between the second power source node and the second node and between the second power source node and the fourth node responsive to the second signal.

2. The amplifier of claim 1, wherein the first signal includes a clamp signal.

3. The amplifier of claim 1, wherein the first and second transistors are off and the third transistor is on at a first period, the first and second transistors are on and the third transistor is on at a second period following to the first period, and the first and second transistors are on and the third transistor is off at a third period following to the second period.

4. The amplifier of claim 1, wherein the third transistor is of a first conductive type, the amplifier further comprising a fourth transistor of a second conductivity different from the first conductivity coupled between the first and third nodes and configured to form the current path between the first and third nodes responsive to the first signal.

5. The amplifier of claim 1, further comprising first and second resistors inserted between the third transistor and the first and second transistors respectively.

6. The amplifier of claim 1, further comprising:

a fourth transistor of a first conductivity type coupled between the first and third nodes and configured to form a second current path between the first and third nodes responsive to a third signal; and

a fifth transistor of a second conductivity different from the first conductivity coupled between the first and third nodes and configured to form the second current path between the first and third nodes responsive to the third signal.

7. The amplifier of claim 6, further comprising a control circuit configured to delay set both of the first signal and second signal high at a first time, the control signal further configured to set the first signal low at a second time and to set the second signal low at third time after the second time.

8. The amplifier of claim 6, further comprising first and second resistors inserted between the first and third nodes where the third transistor is coupled and respective nodes where the fourth and fifth transistors are coupled, respectively.

9. The amplifier of claim 6, wherein the first enable circuit includes transistors of a first conductivity and the second enable circuit includes transistors of a second conductivity.

10. An amplifier, comprising:

a first transistor coupled between first and second nodes;

a second transistor coupled between third and fourth nodes, a control gate of the first transistor being coupled to the third node and a control gate of the second transistor being coupled to the first node;

a first control circuit comprising a first pair of transistors coupled between the first and third nodes and configured to form a first current path between the first and third nodes responsive to a first signal;

a second control circuit comprising a second pair of transistors coupled between the first and third nodes and configured to form a second current path between the first and third nodes responsive to a second signal;

a first enable circuit coupled to the first node and the third node and configured to form a current path between a first power source node and the first node and between the first power source node and the third node; and

a second enable circuit coupled to the first node and the third node and configured to form a current path between a second power source node and the first node and between the second power source node and the third node.

11. The amplifier of claim 10, wherein a first transistor of the first pair of transistors is a first conductive type and a second transistor of the first pair of transistors is a second conductivity type.

12. The amplifier of claim 10, wherein the first enable circuit is configured to form the current path between the first power source node and the first node and between the first power source node and the third node in response to a first enable signal, and wherein the second enable circuit is configured to form the current path between the second power source node and the first node and between the second power source node and the third node in response to a second enable signal.

13. The amplifier of claim 12, wherein the first enable signal is logically inverted as compared with the second enable signal.

14. The amplifier of claim 10, further comprising first and second resistors inserted between the first and third nodes where the first pair of transistors is coupled and respective nodes where the second pair of transistors are coupled, respectively.

15. The amplifier of claim 10, wherein the first and second transistors are off and the first pair of transistors and the second pair of transistor are on at a first period, the first and second transistors are on and the first pair of transistors and the second pair of transistor are on at a second period following to the first period, and the first and second transistors are on and the first pair of transistors and the second pair of transistor are on off at a third period following to the second period.

16. The amplifier of claim 10, wherein, at a fourth period between the second time period and the third period, the first and second transistors are on, the first pair of transistors are on, and the second pair of transistor are off.

17. A method, comprising:

at a first time;

coupling a first node to a second node via a first pair of transistors of a first control circuit of an amplifier in response to a first signal; and

coupling the first node to the second node via a second pair of transistors of a second control circuit of an amplifier in response to a second signal;

at a second time, enabling first and second enable circuits to sense an input signal via a pair of cross-coupled transistors; and

at third time, disabling the first and second control circuits in response to the first and second signals, respectively.

18. The method of claim 17, further comprising at a fourth period, providing a pair of complementary output signals from the first node and from the second node in response to a pair of complementary input signals.

19. The method of claim 17, wherein enabling the first and second enable circuits is in response to complementary first and second enable signals.

20. The method of claim 17, further comprising at a fourth time, disabling the first and second enable circuits.