System and method for adhering a semiconductive wafer to a mobile electrostatic carrier through a vacuum

• US 10,236,202 B2
• Filed: 09/08/2016
• Issued: 03/19/2019
• Est. Priority Date: 11/11/2013
• Status: Active Grant

• Current Assignee: Diablo Capital, Inc.
• Original Assignee: Diablo Capital, Inc.
• Inventors: Smith, Eryn
• Primary Examiner(s): Leja, Ronald W
• Assistant Examiner(s): Clark, Christopher J
• Application Number:
  US15/259,959
• Publication Number:
  US 20160379862A1
• Time in Patent Office: 922 Days
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/6838 with gripping and holding devices using a vacuum; Bernoulli devices

Abstract

A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The MESC uses a plurality of electrostatic field generating (EFG) circuits to generate electrostatic fields across the MESC that allow the MESC to bond to compositional impurities within the semiconductive wafer. A layer of patterned material is superimposed across the bonding surface of MESC so that the cavities integrated into the layer of patterned material are able produce micro-vacuums that further adhere the semiconductive wafer to the MESC.

Claims

1. A system for adhering a semiconductive wafer to a mobile electrostatic carrier (MESC) through a vacuum comprises:

an MESC;

a layer of patterned material;

said layer of patterned material comprises an exposed surface, an unexposed surface, and a plurality of cavities;

said layer of patterned material being superimposed onto a bonding surface of said MESC;

said plurality of cavities being distributed across said layer of patterned material;

each of said plurality of cavities traversing into said layer of patterned material from said exposed surface towards said unexposed surface;

said MESC comprises a doped semiconductive substrate, a plurality of electrostatic field generating (EFG) circuits, and a capacitance charging interface;

said doped semiconductive substrate comprises a first face and a second face;

each of said plurality of EFG circuits comprises a positive pole, a negative pole, and a biased pole;

said plurality of EFG circuits being distributed across said doped semiconductive substrate;

said positive pole and said negative pole being embedded into said doped semiconductive substrate from said first face;

said positive pole and said negative pole being offset from each other across said first face;

an exposed portion of said doped semiconductive substrate being located between said positive pole and said negative pole for each of said plurality of EFG circuits;

said biased pole being said exposed portion of said doped semiconductive substrate; and

said capacitance charging interface being electrically connected to said positive pole, said negative pole, and said biased pole.

2. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1, wherein a cross-section for each of said plurality of cavities is a regular hexagonal shape.

3. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 2, wherein an apothem of said regular hexagonal shape is 50 micrometers.

4. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 2, wherein the layer of patterned material is a honeycomb-shaped structure.

5. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1, wherein said plurality of cavities is offset amongst each other by a 30-micrometer gap.

6. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1, wherein said layer of patterned material is a polymer material.

7. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one positive terminal;

said at least one positive terminal being electrically connected to said positive poles of said plurality of EFG circuits; and

said at least one positive terminal being mounted onto said second face.

8. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one negative terminal;

said at least one negative terminal being electrically connected to said negative poles from said plurality of EFG circuits; and

said at least one negative terminal being mounted onto said second face.

9. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

said capacitance charging interface comprises at least one biasing terminal;

said at least one biasing terminal being electrically connected to said biased poles from said plurality of EFG circuits; and

said at least one biasing terminal being mounted onto said second face.

10. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

said positive pole and said negative pole being flush with said exposed portions of said doped semiconductor substrate;

a planarized surface being formed by said positive poles and said negative poles of said plurality of EFG circuits and said exposed portions of said doped semiconductor substrate;

said planarized surface being said bonding surface of said MESC.

11. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

a polishing film; and

said polishing film being superimposed upon said bonding surface.

12. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

an insulative film; and

said insulative film being positioned between said positive pole and said doped semiconductive substrate.

13. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1 comprises:

an insulative film; and

said insulative film being positioned between said negative pole and said doped semiconductive substrate.

14. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1, wherein said doped semiconductive substrate is made of a p-type semiconductor material.

15. The system for adhering a semiconductive wafer to a MESC through a vacuum as claimed in claim 1, wherein said doped semiconductive substrate is made of an n-type semiconductor material.

16. A method of adhering a semiconductive wafer to a MESC through a vacuum with the system as claimed in claim 1, the method comprises the steps of:

providing a vacuum chamber, wherein the vacuum chamber is initially at a higher ambient pressure;

placing a semiconductive wafer onto the bonding surface of the MESC;

placing the semiconductive wafer and the MESC within the vacuum chamber;

reducing the vacuum chamber from the higher ambient pressure to a lower vacuum pressure;

electrostatically bonding the semiconductive wafer to the MESC by activating a plurality of EFG circuits integrated into the MESC; and

inducing a vacuum seal with each of the plurality of cavities to the semiconductive wafer by returning the vacuum chamber from the lower vacuum pressure to the higher ambient pressure.