Forming an isolation barrier in an isolator

• US 10,236,221 B2
• Filed: 05/19/2017
• Issued: 03/19/2019
• Est. Priority Date: 05/19/2017
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Blennerhassett, Alan John
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/600,678
• Publication Number:
  US 20180337085A1
• Time in Patent Office: 669 Days
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure a pre-formed solid layer of dielectric material is bonded to the substrate over the first transformer coil or capacitive plate. The preformed solid layer is formed from a thick layer of solid dielectric material, which is ground to the required thickness, either prior to being bonded to the circuit substrate, or thereafter. Such techniques result in a thick isolation layer that is formed more quickly and with lower outgassing risk than conventional spin-coating or deposition techniques.

Claims

1. A method of forming a dielectric insulation layer in an integrated isolator circuit, comprising:

providing a pre-formed solid dielectric layer of a first thickness;

creating a thinned dielectric layer of uniform thickness and substantially planar upper and lower surfaces by thinning the pre-formed solid dielectric layer to a target thickness less than the first thickness; and

forming a first electrode set on the thinned dielectric layer.

2. A method according to claim 1, further comprising bonding the pre-formed solid dielectric layer to a partially formed integrated isolator circuit structure having a second electrode set formed on a substrate wafer prior to creating the thinned dielectric layer and forming the first electrode set on the thinned dielectric layer.

3. A method according to claim 1, and further comprising bonding the thinned dielectric layer to a partially formed integrated isolator circuit structure having a second electrode set formed on a substrate wafer prior to forming the first electrode set on the thinned dielectric layer.

4. A method according to claim 1, wherein the pre-formed solid dielectric layer is a crystalline or polycrystalline material.

5. A method according to claim 1, wherein the pre-formed solid dielectric layer comprises fused silica, quartz, aluminum nitride, or silicon.

6. A method according to claim 1, wherein the target thickness is between 20 and 80 microns.

7. A method according to claim 1, wherein the integrated isolator circuit is a digital isolator circuit.

8. A method of fabricating an integrated digital isolator circuit, comprising:

fabricating a first pre-cursor part of the integrated digital isolator circuit by forming a first electrode set on an integrated circuit substrate;

fabricating a second pre-cursor part of the integrated digital isolator circuit by;

processing a pre-formed solid dielectric layer of a greater thickness than is required for electrical isolation in the integrated digital isolator circuit so as to produce a reduced thickness solid dielectric layer of a desired thickness to give a predetermined electrical isolation in dependence on material properties of the pre-formed solid dielectric layer; and

forming a second electrode set on the reduced thickness solid dielectric layer; and

bonding the second pre-cursor part to the first pre-cursor part to obtain the integrated digital isolator circuit.

9. A method according to claim 8, wherein the fabricating of the first pre-cursor part and the second per-cursor part is performed by different fabrication apparatus.

10. A method according to claim 9, wherein the fabricating of the first pre-cursor part and the second per-cursor part is performed by different fabrication apparatus at the same time.

11. A method according to claim 8, further comprising forming a first passivation layer over the first electrode set, the first passivation layer having vias formed therein electrically contacting at least part of the first electrode set.

12. A method according to claim 11, further comprising forming a second passivation layer over the second electrode set, the second passivation layer having vias formed therein electrically contacting at least part of the second electrode set.

13. A method according to claim 8, wherein the first and second electrode sets comprise respective conducting coil structures of a transformer.

14. A method according to claim 8, wherein the first and second electrode sets represent plates of a capacitor.

15. A method according to claim 8, wherein the pre-formed solid dielectric layer comprises fused silica, quartz, aluminum nitride, or silicon.

16. A method of fabricating an integrated isolator circuit, comprising:

forming a first dielectric layer of reduced thickness from a second dielectric layer of a greater thickness than the first dielectric layer;

bonding the first dielectric layer of reduced thickness to a partially formed integrated isolator circuit structure having a first electrode; and

forming a second electrode on the first dielectric layer of reduced thickness.

17. The method of claim 16, wherein the partially formed integrated isolator circuit comprises a passivation layer formed over the first electrode.

18. The method of claim 16, wherein the first dielectric layer has a thickness between 20 to 80 microns.

19. The method of claim 16, wherein the first dielectric layer has substantially planar upper and lower surfaces.