Semiconductor device having oxide semiconductor layer

• US 10,236,303 B2
• Filed: 05/29/2014
• Issued: 03/19/2019
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Komori, Shigeki, Uochi, Hideki, Futamura, Tomoya, Kasahara, Takahiro
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US14/290,216
• Publication Number:
  US 20140264329A1
• Time in Patent Office: 1,755 Days
• Field of Search: 257 59, 257 64- 66, 257 72, 257 79, 257347
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

Claims

1. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a source region and a drain region over the gate insulating layer;

a first metal layer over the source region;

a second metal layer over the drain region; and

a non-single-crystal oxide semiconductor layer over the gate insulating layer, the first metal layer and the second metal layer, the non-single-crystal oxide semiconductor layer overlapping the gate electrode,

wherein each of the source region and the drain region is an oxide semiconductor layer, and

wherein an oxygen concentration in the source region and the drain region is lower than an oxygen concentration in the non-single-crystal oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein each of the non-single-crystal oxide semiconductor layer, the source region, and the drain region is an oxide layer including indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein a side face of the source region and a side face of the drain region are in contact with the non-single-crystal oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the non-single-crystal oxide semiconductor layer is in contact with the gate insulating layer.

5. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a first oxide layer including indium, gallium, and zinc over the gate insulating layer, the first oxide layer partially overlapping the gate electrode;

a second oxide layer including indium, gallium, and zinc over the gate insulating layer, the second oxide layer partially overlapping the gate electrode;

a first metal layer over the first oxide layer;

a second metal layer over the second oxide layer; and

a third oxide layer including indium, gallium, and zinc over the gate insulating layer, the first metal layer and the second metal layer, the third oxide layer overlapping the gate electrode,

wherein an oxygen concentration in the first oxide layer and the second oxide layer is lower than an oxygen concentration in the third oxide layer.

6. The semiconductor device according to claim 5, wherein the third oxide layer is a non-single-crystal oxide semiconductor layer.

7. The semiconductor device according to claim 5, wherein a side face of the first oxide layer and a side face of the second oxide layer are in contact with the third oxide layer.

8. The semiconductor device according to claim 5, wherein the third oxide layer is in contact with the gate insulating layer.

9. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer over the gate electrode;

a first oxide layer including indium, gallium, and zinc over the gate insulating layer, the first oxide layer partially overlapping the gate electrode;

a second oxide layer including indium, gallium, and zinc over the gate insulating layer, the second oxide layer partially overlapping the gate electrode;

a first metal layer over the first oxide layer;

a second metal layer over the second oxide layer;

a third oxide layer including indium, gallium, and zinc over the gate insulating layer, the first metal layer and the second metal layer, the third oxide layer overlapping the gate electrode;

a protective insulating film over the gate insulating layer, the first metal layer, the second metal layer and the third oxide layer; and

a pixel electrode over the protective insulating film, the pixel electrode being electrically connected to the second metal layer,

wherein an oxygen concentration in the first oxide layer and the second oxide layer is lower than an oxygen concentration in the third oxide layer.

10. The semiconductor device according to claim 9, wherein the third oxide layer is a non-single-crystal oxide semiconductor layer.

11. The semiconductor device according to claim 9, wherein a side face of the first oxide layer and a side face of the second oxide layer are in contact with the third oxide layer.

12. The semiconductor device according to claim 9, wherein the third oxide layer is in contact with the gate insulating layer.