Silicon carbide semiconductor device with double trench and method of making same

• US 10,236,348 B2
• Filed: 10/03/2017
• Issued: 03/19/2019
• Est. Priority Date: 11/15/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Tsuji, Takashi
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/724,188
• Publication Number:
  US 20180138273A1
• Time in Patent Office: 532 Days
• CPC Class Codes: H01L 21/047 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A silicon carbide semiconductor device includes an n-type drift layer and a p-type epitaxial base layer deposited on an n-type silicon carbide substrate, as well as first trenches and second trenches. N-type source regions are formed in the surface layer of the p-type epitaxial base layer, in the sidewalls of the first trenches, and in the bottoms of the first trenches. The thickness of the p-type epitaxial base layer is set so that a concentration of ion species or point defects running along dislocations in the p-type epitaxial base layer is so low that regions surrounding the dislocations do not conduct current due to the ion species or the point defects.

Claims

1. A silicon carbide semiconductor device, comprising:

a drift layer of a first conductivity type formed over an entire front surface of a silicon carbide semiconductor substrate of the first conductivity type;

a base layer of a second conductivity type formed over an entire surface layer of the drift layer;

a first trench formed in a surface layer of the base layer;

a second trench of a narrower width than the first trench, formed in the base layer below the first trench, the second trench being formed in a bottom of the first trench and reaching the drift layer;

source regions of the first conductivity type formed in the surface layer of the base layer, on sidewalls of the first trench, and on portions of a bottom surface of the first trench, the source regions being further formed in upper portions of sidewalls of the second trench that are connected to the bottom surface of the first trench, the source regions that are on the sidewalls of the first and second trenches and on the portions of the bottom surface of the first trench being formed only in regions adjacent to the respective sidewalls of the first and second trenches and the portions of the bottom surface of the first trench, thereby leaving the base layer of the second conductivity type between bottom surfaces of the source regions that are formed in the surface layer of the base layer and a top surface of the drift layer;

an impurity region of the second conductivity type selectively formed in the surface layer of the base layer having the source regions formed therein, the impurity region reaching the base layer thereunder;

a gate electrode embedded in the first trench and the second trench with a gate oxide film interposed between the gate electrode and the first and second trenches;

an interlayer insulating film formed covering the gate electrode;

a source electrode formed contacting the impurity region and the source regions; and

a drain electrode formed on a rear surface side of the silicon carbide semiconductor substrate,

wherein a thickness of the base layer is set so that a prescribed vertical distance is provided between the top surface of the drift layer and the bottom surfaces of the source regions in the surface layer of the base layer so as to reduce a concentration of ion species or point defects running along dislocations in the base layer, thereby reducing leakage current due to the ion species or the point defects.

2. The silicon carbide semiconductor device according to claim 1, wherein the thickness of the base layer is greater than or equal to 8 μ

m.

3. The silicon carbide semiconductor device according to claim 1, wherein the thickness of the base layer is greater than or equal to 12 μ

m.

4. A method of manufacturing a silicon carbide semiconductor device, comprising:

layering a drift layer of a first conductivity type over an entire front surface of a silicon carbide semiconductor substrate of the first conductivity type;

layering a base layer of a second conductivity type over an entire surface layer of the drift layer;

forming a first trench in a surface layer of the base layer;

forming a first source region of the first conductivity type in the surface layer of the base layer, on a left sidewall of the first trench, and on a left portion of a bottom surface of the first trench;

forming a second source region of the first conductivity type in the surface layer of the base layer, on a right sidewall of the first trench, and on a right portion of the bottom surface of the first trench;

forming, in a bottom of the first trench, a second trench having a narrower width than the first trench and going through the base layer and reaching the drift layer;

selectively forming, in the surface layer of the base layer having the first and second source regions formed therein, an impurity region of the second conductivity type reaching the base layer thereunder;

forming a gate electrode in the first trench and the second trench with a gate oxide film interposed between the gate electrode and the first and second trenches;

forming an interlayer insulating film covering the gate electrode;

forming a source electrode contacting the first and second source regions and the impurity region; and

forming a drain electrode on a rear surface side of the silicon carbide semiconductor substrate,

wherein the first and second source regions are formed such that the first and second source regions are further present in upper left and right portions of sidewalls of the second trench that are connected to the bottom surface of the first trench, the first and second source regions that are on the sidewalls of the first and second trenches and on the left and right portions of the bottom surface of the first trench being formed only in regions adjacent to the respective sidewalls of the first and second trenches and the left and right portions of the bottom surface of the first trench, thereby leaving the base layer of the second conductivity type between bottom surfaces of the first and second source regions in the surface layer of the base layer and a top surface of the drift layer, and

wherein in the step of layering the base layer, the base layer is layered to such a thickness that a prescribed vertical distance is provided between the top surface of the drift layer and the bottom surfaces of the source regions in the surface layer of the base layer so as to reduce a concentration of ion species or point defects running along dislocations in the base layer after activation of impurities in the first and second source regions, thereby reducing leakage current due to the ion species or the point defects.