Method for manufacturing a semiconductor device

• US 10,236,352 B2
• Filed: 10/05/2017
• Issued: 03/19/2019
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Haase, Robert, Vielemeyer, Martin
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/725,717
• Publication Number:
  US 20180151676A1
• Time in Patent Office: 530 Days
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first side; forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate; forming an insulation structure including at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench; forming a lower conductive structure in the lower portion of the trench; removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in a lower portion of the trench; and forming an upper conductive structure in the upper portion of the trench.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a first side;

forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate;

forming an insulation structure comprising at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench, and a third insulation layer on the second insulation layer;

forming a lower conductive structure in a lower portion of the trench;

removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in the lower portion of the trench;

forming an upper conductive structure in the upper portion of the trench; and

removing the third insulation layer in the upper portion of the trench while leaving the third insulation layer at least partially in the lower portion of the trench.

2. The method of claim 1, wherein the insulation structure is formed such that the first insulation layer covers the bottom and extends from the bottom of the trench to the first side of the semiconductor substrate, and such that the second insulation layer is formed on and covers the first insulation layer at least in the trench, wherein the second insulation layer and the first insulation layer are comprised of different materials.

3. The method of claim 1, wherein the third insulation layer is removed such that an upper end of the third insulation layer is below an upper end of the second insulation layer after the second insulation layer has been removed in the upper portion of the trench.

4. The method of claim 1, further comprising:

forming an insulation plug on the lower conductive structure after the third insulation layer has been removed in the upper portion of the trench and prior to removing the second insulation layer in the upper portion of the trench.

5. The method of claim 4, wherein the insulation plug is formed by deposition of a dielectric material on and/or in the trench.

6. The method of claim 1, wherein the lower conductive structure is formed before the second insulation layer is removed in the upper portion of the trench, and wherein the upper conductive structure is formed in the upper portion of the trench after the second insulation layer is removed in the upper portion of the trench.

7. The method of claim 1, wherein the lower conductive structure and the upper conductive structure are formed in a common process to form a common conductive structure extending from the lower portion to the upper portion of the trench, wherein the common conductive structure comprises a step at a transition between the lower portion and the upper portion of the trench.

8. The method of claim 1, further comprising:

removing the third insulation layer in the upper portion of the trench and partially in the lower portion of the trench so that an upper end of the third insulation layer is recessed relative an upper end of the second insulation layer; and

forming the lower conductive structure in the lower portion of the trench such that the lower conductive structure extends from below the upper end of the third insulation layer to above the upper end of the third insulation layer.

9. The method of claim 8, wherein the lower conductive structure is in contact with the second insulation layer above the upper end of the third insulation layer.

10. The method of claim 1, wherein the insulation structure defines and bounds a space within the trench, wherein removing the second insulation layer in the upper portion of the trench comprises widening the space in the upper portion of the trench, the method further comprising:

filling the lower portion of the space of the trench at least partially with a first conductive material to form the lower conductive structure in the lower portion of the trench; and

filling the upper portion of the space of the trench at least partially with a second conductive material to form the upper conductive structure in the upper portion of the trench.

11. The method of claim 10, wherein one of:

the first conductive material and the second conductive material are the same conductive material;

the first conductive material and the second conductive material comprise a metal, a metal alloy, a metal silicide, doped polysilicon, or a combination thereof,

the first conductive material and the second conductive material are of different conductive materials;

the first conductive material comprises a metal, a metal alloy, a metal silicide, or a combination thereof, and the second conductive material comprises doped polysilicon; and

the first conductive material comprises doped polysilicon, and the second conductive material comprises a metal, a metal alloy, a metal silicide, or combination thereof.

12. The method of claim 1, wherein forming the insulation structure comprises:

oxidising the sidewall and the bottom of the trench to form the first insulation layer, the first insulation layer being formed by a first insulation material;

depositing a second insulation material on the first insulation layer to form the second insulation layer, the second insulation material being different to the first insulation material and selectively etchable with respect to the first insulation material; and

depositing a third insulation material on the second insulation layer to form the third insulation layer.

13. The method of claim 12, wherein the third insulation material is deposited by CVD (chemical vapour deposition), HTO CVD (high temperature oxide CVD), HDP CVD (high-density plasma chemical vapour deposition), TEOS (Tetraethyl Orthosilicate) deposition, PSG (phosphosilicate glass) deposition, or BPSG (borophosphosilicate glass) deposition.

14. The method of claim 12, wherein the second insulation material is an oxygen-resistant material that is impervious to oxygen diffusion.

15. The method of claim 12, wherein the second insulation material is a silicon nitride layer and the second insulation layer is a silicon nitride layer.

16. The method of claim 12, further comprising:

etching the third insulation material selectively to the second insulation material to partially remove the third insulation layer from the first insulation layer and the second insulation layer.

17. The method of claim 1, wherein the trench has an aspect ratio of depth to smallest lateral extension of at least 2:

1.

18. The method of claim 1, further comprising:

forming a doping region in the semiconductor substrate;

forming an electrical connection between the doping region and the lower conductive structure in the trench; and

forming the upper conductive structure in the upper portion of the trench.

19. The method of claim 1, wherein at least one of the lower conductive structure and the upper conductive structure comprises a metal, a metal alloy, a metal silicide, or a combination thereof.

20. A method for manufacturing a semiconductor device, the method comprising:

forming a trench in a semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate;

forming a first insulation layer covering the bottom of the trench and extending from the bottom of the trench along the sidewall of the trench to the first side of the semiconductor substrate;

forming a second insulation layer on the first insulation layer and extending along the first insulation layer to an upper end of the second insulation layer being recessed relative to the first side of the semiconductor substrate, the first insulation layer and the second insulation layer comprising different materials, the upper end of the second insulation layer defining an upper end of a lower portion of the trench;

forming a lower conductive structure in the lower portion of the trench, each of the first and the second insulation layers being arranged between the lower conductive structure and the semiconductor substrate; and

forming an upper conductive structure in an upper portion of the trench above the lower portion, the first insulation layer being arranged between the upper conductive structure and the semiconductor substrate.

21. A method for manufacturing a semiconductor device;

the method comprising;

providing a semiconductor substrate having a first side;

forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate;

forming an insulation structure comprising at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench;

forming a lower conductive structure in a lower portion of the trench;

removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in the lower portion of the trench; and

forming an upper conductive structure in the upper portion of the trench,

wherein the lower conductive structure and the upper conductive structure are formed in a common process to form a common conductive structure extending from the lower portion to the upper portion of the trench, wherein the common conductive structure comprises a step at a transition between the lower portion and the upper portion of the trench.

22. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a first side;

forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate;

forming an insulation structure comprising at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench, and a third insulation layer on the second insulation layer;

forming a lower conductive structure in a lower portion of the trench;

removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in the lower portion of the trench;

forming an upper conductive structure in the upper portion of the trench;

removing the third insulation layer in the upper portion of the trench and partially in the lower portion of the trench so that an upper end of the third insulation layer is recessed relative to an upper end of the second insulation layer; and

forming the lower conductive structure in the lower portion of the trench such that the lower conductive structure extends from below the upper end of the third insulation layer to above the upper end of the third insulation layer.

23. The method of claim 22;

wherein the lower conductive structure is in contact with the second insulation layer above the upper end of the third insulation layer.

24. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a first side;

forming a trench in the semiconductor substrate, the trench having a bottom and a sidewall extending from the bottom to the first side of the semiconductor substrate;

forming an insulation structure comprising at least a first insulation layer and a second insulation layer on the sidewall and the bottom of the trench;

forming a lower conductive structure in a lower portion of the trench;

removing the second insulation layer in an upper portion of the trench while leaving the second insulation layer at least partially in the lower portion of the trench; and

forming an upper conductive structure in the upper portion of the trench, wherein forming the insulation structure comprises;

oxidising the sidewall and the bottom of the trench to form the first insulation layer, the first insulation layer being formed by a first insulation material;

depositing a second insulation material on the first insulation layer to form the second insulation layer, the second insulation material being different to the first insulation material and selectively etchable with respect to the first insulation material; and

depositing a third insulation material on the second insulation layer to form a third insulation layer.

25. The method of claim 24, wherein the third insulation material is deposited by CVD (chemical vapour deposition), HTO CVD (high temperature oxide CVD), HDP CVD (high-density plasma chemical vapour deposition), TEOS (Tetraethyl Orthosilicate) deposition, PSG (phosphosilicate glass) deposition, or BPSG (borophosphosilicate glass) deposition.

26. The method of claim 24, wherein the second insulation material is an oxygen-resistant material that is impervious to oxygen diffusion.

27. The method of claim 24, wherein the second insulation material is a silicon nitride layer and the second insulation layer is a silicon nitride layer.

28. The method of claim 24, further comprising:

etching the third insulation material selectively to the second insulation material to partially remove the third insulation layer from the first insulation layer and the second insulation layer.