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Fabrication of a vertical fin field effect transistor with a reduced contact resistance

  • US 10,236,355 B2
  • Filed: 09/05/2017
  • Issued: 03/19/2019
  • Est. Priority Date: 06/24/2016
  • Status: Active Grant
First Claim
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1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance, comprising:

  • forming a doped region on a substrate;

    forming a plurality of vertical fins on the doped region;

    heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; and

    removing an upper portion of at least one of the plurality of vertical fins and leaving at least another one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of an interface between the doped region and a source/drain contact.

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