Fabrication of a vertical fin field effect transistor with a reduced contact resistance

• US 10,236,355 B2
• Filed: 09/05/2017
• Issued: 03/19/2019
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Yushina, Galina
• Application Number:
  US15/695,688
• Publication Number:
  US 20180012969A1
• Time in Patent Office: 560 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Claims

1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance, comprising:

forming a doped region on a substrate;

forming a plurality of vertical fins on the doped region;

heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; and

removing an upper portion of at least one of the plurality of vertical fins and leaving at least another one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of an interface between the doped region and a source/drain contact.

2. The method of claim 1, wherein the heat treating is at a temperature in the range of about 800°

C. to about 1200°

C.

3. The method of claim 1, wherein the at least one doped extension has a height in the range of about 10 nm to about 40 nm measured from a top surface of the doped region.

4. The method of claim 1, further comprising forming a bottom source/drain contact on the at least one doped extension and a portion of a top surface of the doped region, wherein the at least another one of the plurality of vertical fins on the doped region is not covered by the bottom source/drain contact.

5. The method of claim 1, wherein the dopant concentration in the doped region is in the range of about 1×

10¹⁹ cm<sup>−

3</sup> to about 2×

10²¹ cm<sup>−

3</sup>.

6. The method of claim 1, wherein the plurality of vertical fins are made of a material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), III-V compound semiconductor materials, and II-VI compound semiconductor materials.

7. The method of claim 1, further comprising forming a gate structure on the at least one of the plurality of vertical fins on the doped region, and leaving at least one of the plurality of vertical fins without a gate structure.

8. The method of claim 7, further comprising forming an interlayer dielectric on at least one of the one or more vertical fins with the gate structure and the at least one of the one or more vertical fins without the gate structure;

and

removing a portion of the interlayer dielectric on the at least one of the one or more vertical fins without the gate structure to expose the at least one vertical fin without the gate structure.

9. The method of claim 8, wherein the gate structure includes a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins, and a gate fill layer on the gate dielectric layer.

10. The method of claim 8, wherein the at least one doped extension has a width in the range of about 6 nm to about 20 nm.

11. A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

forming the doped region on a substrate, wherein the doped region has two or more interfacial features that increase the surface area of the doped region, and wherein each of the interfacial features has a width in a range of about 6 nm to about 20 nm, and the interfacial features are separated by a pitch in a range of about 30 nm to about 200 nm;

forming the bottom source/drain contact on at least a portion of the doped region including the two or more interfacial features, wherein the bottom source/drain contact covers the sidewalls of at least two of the two or more interfacial features.

12. The method of claim 11, wherein the doped region and the bottom source/drain contact are electrically coupled together, and the two or more interfacial features provide an increased electrical contact area and a decreased contact resistance between the bottom source/drain contact and the doped region.

13. The method of claim 11, further comprising forming one or more vertical fins on the doped region.

14. The method of claim 13, further comprising forming a top source/drain on at least one of the one or more vertical fins, and a top source/drain contact on the top source/drain.

15. The method of claim 14, wherein the two or more interfacial features that increase the surface area of the interface are doped extensions that extend from the surface of the doped region into the bottom source/drain contact.

16. The method of claim 14, further comprising forming a gate structure on the at least one of the one or more vertical fins.

17. A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

forming a doped region on a substrate

forming two or more doped extensions that extend outward from the top surface of the doped region and two or more vertical fins that extend outward from the top surface of the doped region, wherein the doped extensions and vertical fins are separated by the same pitch;

forming a bottom source/drain contact on at least a portion of the doped region on which the two or more doped extensions are formed, wherein the bottom source/drain contact covers the sidewalls of at least two of the two or more doped extensions.

18. The method of claim 17, wherein the two or more doped extensions each have a width in the range of about 6 nm to about 20 nm.

19. The method of claim 17, wherein the two or more doped extensions each have a height in the range of about 10 nm to about 40 nm measured from a top surface of the doped region.

20. The method of claim 17, further comprising forming a gate structure on at least one of the one or more vertical fins to form the vertical fin field effect transistor.