Dynamic error vector magnitude duty cycle correction

• US 10,236,829 B2
• Filed: 10/19/2017
• Issued: 03/19/2019
• Est. Priority Date: 09/19/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Lam, Lui, Doherty, Mark M.
• Primary Examiner(s): Nguyen, Hieu P
• Application Number:
  US15/788,025
• Publication Number:
  US 20180138861A1
• Time in Patent Office: 516 Days
• Field of Search: 330136, 330285, 330296, 330289
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/429 Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 1/04 Circuits

Abstract

Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Claims

1. A method of biasing a power amplifier arranged to amplify a radio frequency signal, the method comprising:

low pass filtering an indication of duty cycle of the power amplifier to generate a correction signal, the indication of duty cycle being a binary signal;

generating a bias signal based at least partly on the correction signal; and

biasing the power amplifier with the bias signal so as to compensate for variation in gain of the power amplifier due to a change in the duty cycle of the power amplifier.

2. The method of claim 1 further comprising transmitting, via an antenna of a mobile device, an amplified radio frequency generated by the power amplifier.

3. The method of claim 1 further comprising amplifying a wireless local area network signal with the power amplifier.

4. The method of claim 1 wherein the low pass filtering includes charging a capacitor.

5. The method of claim 1 wherein the low pass filtering includes integrating the indication of duty cycle of the power amplifier.

6. The method of claim 1 wherein the generating the bias signal includes adjusting an adjustable current source based on the correction signal.

7. A method of biasing a power amplifier arranged to amplify a radio frequency signal, the method comprising:

low pass filtering an indication of duty cycle of the power amplifier to generate a correction signal;

generating a bias signal based at least partly on the correction signal, the generating being performed such that changes in the bias signal are inversely proportional to changes in the duty cycle of the power amplifier; and

biasing the power amplifier with the bias signal so as to compensate for variation in gain of the power amplifier due to a change in the duty cycle of the power amplifier.

8. The method of claim 7 wherein the indication of duty cycle is a binary signal.

9. The method of claim 7 wherein the low pass filtering includes integrating the indication of duty cycle of the power amplifier.

10. A power amplifier system with dynamic error vector magnitude compensation, the power amplifier system comprising:

a power amplifier configured to amplify a radio frequency signal;

a duty cycle tracking circuit configured to track a duty cycle of the power amplifier and to provide a signal representative of the duty cycle of the power amplifier; and

a bias circuit configured to generate a bias signal based at least partly on the signal representative of the duty cycle of the power amplifier such that changes in the bias signal have an inverse relationship with changes in the duty cycle of the power amplifiers and to bias the power amplifier using the bias signal so as to compensate for dynamic error vector magnitude.

11. The power amplifier system of claim 10 wherein the power amplifier includes a power amplifier bipolar transistor, and the bias circuit includes a reference bipolar transistor having a base electrically connected to a base of the power amplifier bipolar transistor.

12. The power amplifier system of claim 11 wherein the bias circuit includes a base current helper bipolar transistor having an emitter electrically connected to the base of the reference bipolar transistor.

13. The power amplifier system of claim 10 wherein the bias circuit includes an adjustable current source configured to receive the signal representative of duty cycle.

14. The power amplifier system of claim 10 wherein the duty cycle tracking circuit is configured to receive an enable signal for the power amplifier and to generate the signal representative of the duty cycle of the power amplifier based on the enable signal.

15. The power amplifier system of claim 10 wherein the radio frequency signal is a wireless local area network signal.

16. A wireless communication device with dynamic error vector magnitude compensation and arranged for communication using a wireless local area network protocol, the wireless communication device comprising:

a power amplifier configured to provide a wireless local area network signal;

a duty cycle tracking circuit configured to generate a signal representative of the duty cycle of the power amplifier;

a bias circuit configured to generate a bias signal based at least partly on the signal representative of the duty cycle of the power amplifier such that changes in the bias signal have an inverse relationship with changes in the duty cycle of the power amplifier, and the bias circuit is configured to bias the power amplifier using the bias signal so as to compensate for dynamic error vector magnitude; and

an antenna configured to transmit the wireless local area network signal.

17. The wireless communication device of claim 16 wherein the power amplifier includes a power amplifier bipolar transistor, and the bias circuit includes a reference bipolar transistor having a base electrically connected to a base of the power amplifier bipolar transistor.

18. The wireless communication device of claim 16 wherein the power amplifier is on a GaAs die.

19. The wireless communication device of claim 16 wherein the power amplifier is on a SiGe die.

20. The wireless communication device of claim 16 wherein the signal representative of the duty cycle of the power amplifier is a binary signal.