Multilayer electronic structures with embedded filters

• US 10,236,854 B2
• Filed: 04/11/2018
• Issued: 03/19/2019
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
• Inventors: Hurwitz, Dror, Huang, Alex
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/950,886
• Publication Number:
  US 20180367114A1
• Time in Patent Office: 342 Days
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 2001/0085 Multilayer, e.g. LTCC, HTCC, green sheets
• CPC Class Codes: H03H 3/00 Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/0138 Electrical filters or coupling circuits

Abstract

A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist stripping away the photoresist and laminating.

Claims

1. A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising:

at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises;

at least one capacitor coupled with at least one inductor,

the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode; and

depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning photoresist with a via post over said ceramic dielectric layer;

sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist, stripping away the photoresist and laminating.

2. The method of claim 1, wherein the dielectric material is selected from the group consisting of Ta2O5, TiO₂, BaO₄SrTi and Al₂O₃.

3. The method of claim 1, further comprises depositing a lower layer of electrode on the feature of the feature layer prior to depositing the ceramic dielectric, said lower layer of electrode being fabricated from a material selected from the group consisting of gold, platinum and tantalum.

4. The method of claim 1 further comprising depositing an upper electrode over the ceramic dielectric layer selected from the group consisting of gold, platinum and tantalum, depositing accurately sized copper via posts over the upper electrode, and selectively removing excess upper electrode, dielectric and lower electrode to control size of the capacitor.

5. The method of claim 4 wherein the excess upper electrode, the dielectric and the lower electrode are removed by plasma etching.

6. The method of claim 1, wherein the capacitors are fabricated by a method comprising the steps of:

(i) procuring a carrier;

(ii) depositing a barrier layer;

(iii) thinning barrier layer;

(iv) depositing a thin layer of copper above the barrier layer;

(v) depositing a first layer of electrode material;

(vi) depositing a layer of dielectric material;

(vii) depositing a second layer of electrode material;

(viii) depositing an upper copper layer over the second electrode,

(ix) applying photoresist over the upper copper layer and patterning;

(x) etching away exposed copper of the upper copper layer;

(xi) etching away exposed material of the second electrode layer, exposed dielectric material in the layer of dielectric material and exposed material in the first layer of electrode, and

(xii) stripping away the photoresist.

7. The method of claim 6, wherein step (vi) of depositing a layer of dielectric material comprises sputtering a layer of ceramic, and further comprises previously or subsequently depositing a layer of aluminum, and then oxidizing the aluminum to less dense aluminum-oxide, thereby growing aluminum-oxide into defects in the layer of ceramic and sealing the defects.

8. The method of claim 7 wherein the carrier is selected from the group consisting of a sacrificial copper substrate and a copper carrier with a quick release thin film of copper appended thereto.

9. The method of claim 1 wherein inductors are fabricated by depositing a copper seed layer over a dielectric polymer that is thinned to expose at least one copper via, thereby providing conductive connection;

laying down a layer of photoresist;

patterning the photoresist to create a shaped via that is elongated;

depositing copper into the photoresist to create an inductor;

stripping away the photoresist;

etching away the seed layer, and

laminating.

10. The method of claim 9 wherein a titanium seed layer is deposited prior to the copper seed layer.

11. The method of claim 10 wherein inductors are fabricated by depositing a copper seed layer over a dielectric polymer that is thinned to expose at least one copper via, thereby providing conductive connection;

laying down a layer of photoresist;

patterning the photoresist to create a spiral feature;

depositing copper into the photoresist to create an inductor;

stripping away the photoresist;

and etching away the seed layer.

12. The method of claim 11, further comprising laminating.

13. The method of claim 11 wherein a titanium seed layer is deposited prior to the copper seed layer.

14. The method of claim 13 further comprising:

embedding the array of filters in a polymer matrix;

thinning to expose ends of vias;

applying terminations by laying down photoresist on each side of the thinned polymer matrix;

deposing copper pads into the pattern of photoresist;

stripping away the photoresist;

laying down soldermask between the copper pads, and

applying a protective coating.

15. The method of claim 14, wherein said protective coating is selected from ENEPIG and an organic varnish.

16. The composite electronic structure of claim 1, wherein the at least one capacitor and the at least one inductor are coupled in series.

17. The composite electronic structure of claim 1, comprising at least a second feature layer over the via layer and wherein the at least one capacitor and the at least one inductor are coupled in parallel via the feature layer.

18. The composite electronic structure of claim 1, wherein the at least one inductor is fabricated in the feature layer.

19. The multilayer composite electronic structure of claim 18, wherein the at least one inductor is spirally coiled.

20. The multilayer composite electronic structure of claim 1, wherein the at least one inductor is fabricated in a via layer.

21. The multilayer composite electronic structure of claim 1, wherein said at least one inductor and said at least one capacitor provide a filter, said filter being selected from the group consisting of basic LC low pass filters, LC high pass filters, LC series band pass filters, LC parallel band pass filters and Low Pass Parallel-Chebyshev filters.

22. The multilayer composite electronic structure of claim 1, wherein the polymer matrix is further characterized by at least one of the following limitations:

(a) said polymer matrix comprises a polymer selected from the group comprising polyimides, epoxies, BT (Bismaleimide/Triazine) and their blends;

(b) said polymer matrix further comprises glass fibers; and

(c) said polymer matrix further comprises inorganic particulate fillers having mean particle size of between 0.5 microns and 30 microns and between 15% and 30% of particulate by weight.