Flash memory apparatus and storage management method for flash memory

• US 10,236,908 B2
• Filed: 04/25/2017
• Issued: 03/19/2019
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion Technology Corporation)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion Technology Corporation)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/495,992
• Publication Number:
  US 20170317693A1
• Time in Patent Office: 693 Days
• Field of Search: 714773, 714747, 714718, 714704
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: H03M 13/098 using single parity bit
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Claims

1. A flash memory apparatus, comprising:

a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and

a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks;

wherein when completing program of the plurality of single-level-cell blocks, controlling the flash memory module to perform an internal copy operation to program the at least one multiple-level-cell block of the flash memory module according to the plurality of single-level-cell blocks of the flash memory module.

2. The flash memory apparatus of claim 1, wherein a cell of the at least one multiple-level-cell block is capable of storing information of 2^N bits, and N is an integer which is equal to or greater than 2;

the plurality of single-level-cell blocks are N single-level-cell blocks, and the flash memory controller is arranged for classifying the data to be programmed into N groups of data to respectively program the N groups of data into the N single-level-cell blocks.

3. The flash memory apparatus of claim 2, wherein N is equal to 3, and the at least one multiple-level-cell block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

4. The flash memory apparatus of claim 2, wherein when programming a group of data to a single-level-cell block, the flash memory controller is arranged for sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block into a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines, for respectively executing different Reed-Solomon encoding operations upon the plurality of odd groups of word lines and the plurality of even groups of word lines to generate a first parity check code of the odd groups of word lines and a second parity check code of the even groups of word lines, for programming and storing the first parity check code at last data pages of a last word line of a last group among the plurality of odd groups of word lines, and for programming and storing the second parity check code at last data pages of a last word line of a last group among the plurality of even groups of word lines.

5. The flash memory apparatus of claim 1, wherein when performing memory garbage collection, the flash memory controller is arranged for externally reading out and retrieving data from the plurality of single-level-cell blocks or from the at least one multiple-level-cell block for re-encoding and re-programming the read out and retrieved data.

6. The flash memory apparatus of claim 1, wherein when programming data into a single-level-cell block and shutdown occurring, the flash memory controller is arranged to read back data from the single-level-cell block and re-encode and program the read back data into another single-level-cell block.

7. The flash memory apparatus of claim 1, wherein when programming data into the at least one multiple-level cell block and shutdown occurring, the flash memory module is arranged to discard data stored by the at least one multiple-level cell block and perform the internal copy operation to copy and program data from the plurality of single-level-cell blocks into the at least one multiple-level cell block.

8. The flash memory apparatus of claim 1, wherein when programming data into the plurality of single-level-cell blocks, the flash memory controller is arranged to program data into the plurality of single-level-cell blocks according to a randomizer seed rule of the at least one multiple-level cell block.

17. The flash memory apparatus of claim 1, wherein the flash memory module is controlled to perform the internal copy operation by sequentially reading the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks and then writing the groups of data and the corresponding parity check code, read from the plurality of single-level-cell blocks, to the at least one multiple-level-cell block according to an order of storing the groups of data and the corresponding parity check code in the plurality of single-level-cell blocks.

9. A flash memory storage management method, comprising:

providing a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block;

classifying data to be programmed into a plurality of groups of data;

respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; and

when completing program of the plurality of single-level-cell blocks, controlling the flash memory module to perform an internal copy operation to program the at least one multiple-level-cell block of the flash memory module according to the plurality of single-level-cell blocks of the flash memory module.

10. The method of claim 9, wherein a cell of the at least one multiple-level-cell block is capable of storing information of 2^N bits, and N is an integer which is equal to or greater than 2;

the plurality of single-level-cell blocks are N single-level-cell blocks, and the classifying step comprises;

classifying the data to be programmed into N groups of data to respectively program the N groups of data into the N single-level-cell blocks.

11. The method of claim 10, wherein N is equal to 3, and the at least one multiple-level-cell block is a triple-level-cell block, and the step of classifying the data to be programmed into N groups of data comprises:

classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

12. The method of claim 10, wherein the executing step comprise:

when programming a group of data to a single-level-cell block, sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block into a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines;

respectively executing different Reed-Solomon encoding operations upon the plurality of odd groups of word lines and the plurality of even groups of word lines to generate a first parity check code of the odd groups of word lines and a second parity check code of the even groups of word lines, programming and storing the first parity check code at last data pages of a last word line of a last group among the plurality of odd groups of word lines; and

programming and storing the second parity check code at last data pages of a last word line of a last group among the plurality of even groups of word lines.

13. The method of claim 9, further comprising:

when performing memory garbage collection, reading out and retrieving data from the plurality of single-level-cell blocks or from the at least one multiple-level-cell block for re-encoding and re-programming the read out and retrieved data.

14. The method of claim 9, further comprising:

when programming data into a single-level-cell block and shutdown occurring, reading back data from the single-level-cell block and re-encode and program the read back data into another single-level-cell block.

15. The method of claim 9, further comprising:

when programming data into the at least one multiple-level cell block and shutdown occurring, discarding data stored by the at least one multiple-level cell block and performing the internal copy operation to copy and program data from the plurality of single-level-cell blocks into the at least one multiple-level cell block.

16. The method of claim 9, further comprising:

when programming data into the plurality of single-level-cell blocks, programming data into the plurality of single-level-cell blocks according to a randomizer seed rule of the at least one multiple-level cell block.

18. The flash memory storage management method of claim 9, wherein the step of controlling the flash memory module to perform the internal copy operation comprises:

controlling the flash memory module to;

sequentially reading the groups of data and the corresponding parity check code from the plurality of single-level-cell blocks; and

writing the groups of data and the corresponding parity check code, read from the plurality of single-level-cell blocks, to the at least one multiple-level-cell block according to an order of storing the groups of data and the corresponding parity check code in the plurality of single-level-cell blocks.

19. A flash memory controller coupled to a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block, and the flash memory controller comprises:

a plurality of channels respectively connected to the flash memory module; and

the flash memory controller is configured for;

classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; and

when completing program of the plurality of single-level-cell blocks, controlling the flash memory module to perform an internal copy operation to program the at least one multiple-level-cell block of the flash memory module according to the plurality of single-level-cell blocks of the flash memory module.