Bit-order modification for different memory areas of a storage device

• US 10,236,909 B2
• Filed: 03/31/2017
• Issued: 03/19/2019
• Est. Priority Date: 03/31/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Rom, Rami, Goldenberg, Idan, Bazarsky, Alexander, Sharon, Eran, Zamir, Ran, Alrod, Idan, Achtenberg, Stella
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/475,666
• Publication Number:
  US 20180287632A1
• Time in Patent Office: 718 Days
• Field of Search: 714763, 714718, 714768, 714770, 714773, 714786, 714799, 714 622, 714 624, 714 25, 365200, 365201, 36518509
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/1125 using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Claims

1. A bit-order modification method comprising:

encoding, with at least one controller, a plurality of information bits using a codebook to generate an original codeword, wherein the plurality of information bits are to be programmed into a memory area of memory of a storage device, the memory area having an associated set of bad storage locations;

modifying, with the at least one controller, the original codeword to generate a modified codeword by switching a bad bit of the original codeword with a good bit of the original codeword; and

programming, with the at least one controller, the modified codeword into the memory area.

2. The bit order modification method of claim 1, wherein the bad bit of the original codeword corresponds to a check node that is one of a predetermined number of check nodes of the codebook connected to the most bad variable nodes of the codebook.

3. The bit order modification method of claim 1, wherein the bad bit of the original codeword corresponds to a check node of the codebook that is connected to a number of bad variable nodes exceeding a threshold or within a predetermined range.

4. The bit-order modification method of claim 1, wherein the bad bit of the original codeword corresponds to a variable node participating in a minimal cycle of the codebook that is one of a predetermined number of minimal cycles having the most participating bad variable nodes.

5. The bit-order modification method of claim 1, wherein the bad bit of the original codeword corresponds to a variable node participating in a minimal cycle of the codebook that is one of a predetermined number of minimal cycles having either the smallest difference between cycle length and number of participating bad variable nodes or the largest ratio of number of participating bad variable nodes to cycle length.

6. The bit order modification method of claim 1, wherein the bad bit of the original codeword corresponds to a variable node participating in a minimal cycle of the codebook that is one of a predetermined number of minimal cycles having either the smallest difference between number of participating bad variable nodes and total number of participating variable nodes or largest ratio of number of participating bad variable nodes to total number of participating variable nodes.

7. The bit order modification method of claim 1, wherein modifying the original codeword comprises switching good bits and bad bits across sub-codeword portions of the original codeword to generate the modified codeword, wherein the modified codeword comprises an equalized distribution of bad bits across sub-codeword portions of the modified codeword in response to the switching of good bits and bad bits.

8. The bit-order modification method of claim 1, wherein the plurality of different memory areas comprises different dies, different planes, different blocks, different pages, or different segments of the memory.

9. A bit re-ordering configuration method comprising:

identifying, with at least one controller, bad storage location information of a memory area of a plurality of different memory areas of a memory of a storage device;

identifying, with the at least one controller, a codebook that the storage device is configured to use to encode a plurality of information bits to generate an original codeword;

generating, with the at least one controller, a bit-order modification configuration based on the bad storage location information of the memory area and the codebook; and

configuring a bit order modification module of the storage device with the bit-order modification configuration, wherein the bit order modification module, upon being configured with the bit-order modification configuration, is configured to modify the original codeword to generate a modified codeword to be stored in the memory area according to the bit-order modification configuration.

10. The bit re-ordering configuration method of claim 9, further comprising:

identifying, with the at least one controller, a check node of the codebook based on numbers of bad variable nodes connected to check nodes of the codebook; and

identifying, with the at least one controller, at least one bad bit of the original codeword to be stored in the memory area to switch with at least one good bit of the original codeword for the bit-order modification configuration based on the identified check node.

11. The bit re-ordering configuration method of claim 10, wherein selecting the check node is based on identifying, with the at least one controller, that the number of bad variable nodes connected to the check node exceeds a threshold number.

12. The bit re-ordering configuration method of claim 10, wherein selecting the check node is based on identifying, with the at least one controller, that the check node is one of a predetermined number of check nodes connected to the most bad variable nodes.

13. The bit re-ordering configuration method of claim 9, further comprising:

identifying, with the at least one controller, a bad variable node of the codebook based on numbers of bad variable nodes participating in minimal cycles of the codebook; and

identifying, with the at least one controller, a bad bit of the original codeword to switch with a good bit of the original codeword, wherein the bad bit corresponds to the bad variable node.

14. The bit re-ordering configuration method of claim 13, further comprising:

identifying, with the at least one controller, a minimal cycle in which the bad variable node is participating, the identifying being based on a criterion associated with at least one of;

a number of bad variable nodes participating in the minimal cycle, a length of the minimal cycle, or a total number of variable nodes participating in the minimal cycle.

15. The bit re-ordering configuration method of claim 9, wherein generating the bit-order modification configuration comprises identifying bad bits to switch with good bits across sub-codeword portions of the original codeword, wherein a result of the switching of the bad bits with the good bits provides an equalized distribution of bad bits across the sub-codeword portions.

16. The bit re-ordering configuration method of claim 9, wherein the plurality of different memory areas comprises different dies, different planes, different blocks, different pages, or different segments of the memory.

17. A storage device comprising:

a memory comprising a plurality of different memory areas; and

a controller configured to;

generate a first original codeword using a codebook, the first original codeword comprising a first plurality of information bits to be stored in a first memory area of the plurality of different memory areas;

change a bit order of the first original codeword to generate a first modified codeword, wherein the bit order of the first original codeword is changed according to a first bit modification configuration corresponding to a first plurality of bad storage locations of the first memory area;

generate a second original codeword using the codebook, the second original codeword comprising a second plurality of information bits to be stored in a second memory area of the plurality of different memory areas;

change a bit order of the second original codeword to generate a second modified codeword, wherein the bit order of the second codeword is changed according to a second bit modification configuration corresponding to a second plurality of bad storage locations of the second memory area, and wherein the second bit modification configuration is different than the first bit modification configuration; and

program the first modified codeword in the first memory area and the second modified codeword in the second memory area.

18. The storage device of claim 17, wherein the controller is configured to maintain a respective bit modification configuration for each memory area of the plurality of different memory areas of the memory.

19. The storage device of claim 17, wherein the plurality of different memory areas comprises different dies, different planes, different blocks, different pages, or different segments of the memory.

20. A storage device comprising:

a memory comprising a plurality of different memory areas;

means for generating a first original codeword using a codebook, the first original codeword comprising a first plurality of information bits to be stored in a first memory area of the plurality of different memory areas;

means for changing a bit order of the first original codeword to generate a first modified codeword, wherein the bit order of the first original codeword is changed according to a first bit modification configuration corresponding to a first plurality of bad storage locations of the first memory area;

means for generating a second original codeword using the codebook, the second original codeword comprising a second plurality of information bits to be stored in a second memory area of the plurality of different memory areas;

means for changing a bit order of the second original codeword to generate a second modified codeword, wherein the bit order of the second original codeword is changed according to a second bit modification configuration corresponding to a second plurality of bad storage locations of the second memory area, and wherein the second bit modification configuration is different than the first bit modification configuration; and

means for programming the first modified codeword in the first memory area and the second modified codeword in the second memory area.