Dynamically changing data access bandwidth by selectively enabling and disabling data links

• US 10,241,563 B2
• Filed: 07/19/2016
• Issued: 03/26/2019
• Est. Priority Date: 07/12/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Harrington, Cheri L
• Application Number:
  US15/214,266
• Publication Number:
  US 20160328008A1
• Time in Patent Office: 980 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Claims

1. A method of switching between a first mode of operation and a second mode of operation of an integrated circuit device, the method comprising:

transferring data during the first mode via each link of a plurality of links;

disabling each link of a first subset of the plurality of links during the second mode;

transferring data during the second mode via each link of a second subset of the plurality of links that is not disabled, wherein a common signaling rate is employed for the data transfers via the second subset of the plurality of links during the first mode and the second mode; and

updating at least one timing adjustment value for the disabled first subset of the plurality of links during the second mode while the second subset of the plurality of links is enabled, wherein the at least one updated timing adjustment value for the disabled first subset of the plurality of links is based on first calibration information generated to calibrate the first subset of the plurality of links during the first mode and second calibration information generated to calibrate the enabled second subset of the plurality of links during the second mode.

2. The method of claim 1, further comprising:

transferring control information during the first mode via each link of a plurality of control links;

disabling each link of a first subset of the plurality of control links during the second mode;

transferring the control information during the second mode via each link of a second subset of the plurality of control links that is not disabled; and

updating at least one timing adjustment value for the disabled first subset of the plurality of control links during the second mode while the second subset of the plurality of control links is enabled.

3. The method of claim 1, wherein the first calibration information is established before disabling each link of a first subset of the plurality of links.

4. The method of claim 2, wherein establishing the first calibration information comprises:

transmitting calibration data over the enabled first subset of the plurality of links; and

,

generating the first calibration information to update the at least one timing adjustment value based on the transmission of the calibration data over the enabled first subset of the plurality of links.

5. The method of claim 1, wherein the updating of the at least one timing adjustment value for the first subset of the plurality of links during the second mode is performed:

after receiving an indication that a transition from the second mode to the first mode is to occur; and

,

before the transition from the second mode to the first mode.

6. A first integrated circuit device comprising:

a plurality of driver circuits to transfer data to a second integrated circuit device via a plurality of signaling links;

a steering circuit to select between concurrently routing the data across all of the driver circuits if all of the driver circuits are enabled and employing at least partial serialization to route the data to a first subset of the driver circuits if a second subset of the driver circuits is disabled;

a control circuit to transfer control information between the first integrated circuit device and the second integrated circuit device, wherein the control information provides an indication of how many of the signaling links are employed to transfer the data; and

a calibration circuit to update, while the second subset of the driver circuits is disabled, at least one timing adjustment value for the disabled second subset of the driver circuits based on first calibration information generated to calibrate the first subset of the driver circuits while the second subset of the driver circuits is disabled and second calibration information generated to calibrate the second subset of the driver circuits while the second subset of the driver circuits is enabled.

7. The integrated circuit device of claim 6, wherein:

the first integrated circuit device comprises a memory controller device;

the second integrated circuit device comprises a memory device; and

,

the transfer of the control information comprises transmitting the control information to the memory device.

8. The integrated circuit device of claim 7, wherein the control circuit generates the control information as a result of receiving a signal that indicates that the first integrated circuit device is transitioning between a lower power mode and a higher power mode.

9. The integrated circuit device of claim 7, wherein:

the control circuit generates control signals for enabling and disabling the driver circuits and for controlling the steering circuit; and

,

the control signals are generated as a result of receiving a signal that indicates that the first integrated circuit device is transitioning between a lower power mode and a higher power mode.

10. The integrated circuit device of claim 9, wherein the driver circuits are individually enabled based on the control signals.

11. The integrated circuit device of claim 6, wherein a relative value function is used to calculate the at least one timing adjustment value.

12. The integrated circuit device of claim 6, wherein:

the first integrated circuit device comprises a memory device;

the second integrated circuit device comprises a memory controller device; and

,

the transfer of the control information comprises receiving the control information from the memory controller device.

13. The integrated circuit device of claim 6, wherein the control circuit generates, based on the control information, control signals for enabling and disabling the driver circuits and for controlling the steering circuit.

14. The integrated circuit device of claim 6, wherein the control information is transferred via at least one sideband link.

15. The integrated circuit device of claim 6, wherein the control information comprises an opcode.

16. A method for transferring data from a first integrated circuit device to a second integrated circuit device via a plurality of driver circuits that drive a plurality of signaling links, the method of comprising:

selecting between concurrently routing the data across all of the driver circuits if all of the driver circuits are enabled and employing at least partial serialization to route the data to a first subset of the driver circuits if a second subset of the driver circuits is disabled;

transferring control information between the first integrated circuit device and the second integrated circuit device, wherein the control information provides an indication of how many of the signaling links are employed to transfer the data; and

updating, while the first subset of the driver circuits is enabled, at least one timing adjustment value for the disabled second subset of the driver circuits based on based on first calibration information generated to calibrate the first subset of the driver circuits while the second subset of the driver circuits is disabled and second calibration information generated to calibrate the second subset of the driver circuits while the second subset of the driver circuits is enabled.

17. The method of claim 16, further comprising generating the control information as a result of receiving a signal that indicates that the first integrated circuit device is transitioning between a lower power mode and a higher power mode.

18. The method of claim 16, further comprising enabling and disabling the driver circuits and controlling the selection based on a signal that indicates that the first integrated circuit device is transitioning between a lower power mode and a higher power mode.

19. The method of claim 16, further comprising enabling and disabling the driver circuits and controlling the selection based on the control information.

20. The method of claim 16, wherein a relative value function is used to calculate the at least one timing adjustment value.